Makefile: expand dependencies
- by Danyel
First off, the title is very generic because there are just tons of ways of how to possibly solve this. However, I'm looking for a clean and neat way.
Situation:
I have two equal object files foo.o and foo-pi.o, the latter of which is position-independent (compiled with -fPIC). Both depend on foo.h and bar.h.
Problem:
How do I, without code duplication, declare dependency of all foo*.o to bar.h?
Solutions so far:
$(shell bash -c 'echo -ne foo{-pi,}.o'}: bar.h
$(addsuffix .o, $(addprefix fo, o-pi o)): bar.h
The first solution is not portable on systems that don't support bash, the second is a dirty solution since I could not figure out how to use empty strings in addprefix.
