how this scaling down for css code is worked?
- by harris
this is a code for scaling down for css.
i was wondering, how this worked. please someone explain to me part by part.
thank you very much.
/* ======================================================================== /
/ Copyright (C) 2000 - 2009 ND-Tech. Co., Ltd. /
/ All Rights Reserved. /
/ ======================================================================== /
/ Project : ScaleDown Created : 31-AUG-2009 /
/ File : main.c Contact : [email protected] /
/ ======================================================================== /
/ You are free to use or modify this code to the following restrictions: /
/ Acknowledge ND Tech. Co. Ltd. /
/ Or, put "Parts of code by ND Tech. Co., Ltd." /
/ Or, leave this header as it is. /
/ in somewhere in your code. /
/ ======================================================================== */
include "vm3224k.h"
define CE0CTL *(volatile int *)(0x01800008)
define CE2CTL *(volatile int *)(0x01800010)
define SDCTL *(volatile int *)(0x01800018)
define LED *(volatile short *)(0x90080000)
// Definitions for async access(change as you wish)
define WSU (2<<28) // Write Setup : 0-15
define WST (8<<22) // Write Strobe: 0-63
define WHD (2<<20) // Write Hold : 0-3
define RSU (2<<16) // Read Setup : 0-15
define TA (3<<14) // Turn Around : 0-3
define RST (8<<8) // Read Strobe : 0-63
define RHD (2<<0) // Read Hold : 0-3
define MTYPE (2<<4)
/* EDMA Registers */
define PaRAM_OPT 0 // Options
define PaRAM_SRC 1 // Source Address
define PaRAM_CNT 2 // Frame count, Element count
define PaRAM_DST 3 // Destination Address
define PaRAM_IDX 4 // Frame index, Element index
define PaRAM_RDL 5 // Element count reload, Link address
define EDMA_CIPR *(volatile int *)0x01A0FFE4 // EDMA Channel interrupt pending low register
define EDMA_CIER *(volatile int *)0x01A0FFE8 // EDMA Channel interrupt enable low register
define EDMA_CCER *(volatile int *)0x01A0FFEC // EDMA Channel chain enable register
define EDMA_ER *(volatile int *)0x01A0FFF0 // EDMA Event low register
define EDMA_EER *(volatile int *)0x01A0FFF4 // EDMA Event enable low register
define EDMA_ECR *(volatile int *)0x01A0FFF8 // EDMA Event clear low register
define EDMA_ESR *(volatile int *)0x01A0FFFC // EDMA Event set low register
define PRI (2<<29) // 1:High priority, 2:Low priority
define ESIZE (1<<27) // 0:32bit, 1:16bit, 2:8bit, 3:reserved
define DS2 (0<<26) // 1:2-Dimensional
define SUM (0<<24) // 0:no update, 1:increment, 2:decrement, 3:by index
define DD2 (0<<23) // 1:2-Dimensional
define DUM (0<<21) // 0:no update, 1:increment, 2:decrement, 3:by index
define TCINT (1<<20) // 0:disable, 1:enable
define TCC (8<<16) // 4 bit code
define LINK (0<<1) // 0:disable, 1:enable
define FS (1<<0) // 0:element, 1:frame
define OptionField_0 (PRI|ESIZE|DS2|SUM|DD2|DUM|TCINT|TCC|LINK|FS)
define DD2_1 (1<<23) // 1:2-Dimensional
define DUM_1 (1<<21) // 0:no update, 1:increment, 2:decrement, 3:by index
define TCC_1 (9<<16) // 4 bit code
define OptionField_1 (PRI|ESIZE|DS2|SUM|DD2_1|DUM_1|TCINT|TCC_1|LINK|FS)
define TCC_2 (10<<16)// 4 bit code
define OptionField_2 (PRI|ESIZE|DS2|SUM|DD2|DUM|TCINT|TCC_2|LINK|FS)
define DS2_3 (1<<26) // 1:2-Dimensional
define SUM_3 (1<<24) // 0:no update, 1:increment, 2:decrement, 3:by index
define TCC_3 (11<<16)// 4 bit code
define OptionField_3 (PRI|ESIZE|DS2_3|SUM_3|DD2|DUM|TCINT|TCC_3|LINK|FS)
pragma DATA_SECTION ( lcd,".sdram" )
pragma DATA_SECTION ( cam,".sdram" )
pragma DATA_SECTION ( rgb,".sdram" )
pragma DATA_SECTION ( u,".sdram" )
extern cregister volatile unsigned int IER;
extern cregister volatile unsigned int CSR;
short camcode = 0x08000;
short lcdcode = 0x00000;
short lcd[2][240][320];
short cam[2][240][320];
short rgb[64][32][32];
short bufsel;
int *Cevent,*Levent,*CLink,flag=1;
unsigned char v[240][160],out_y[120][160];
unsigned char y[240][320],out_u[120][80];
unsigned char u[240][160],out_v[120][80];
void PLL6713()
{
int i;
// CPU Clock Input : 50MHz
*(volatile int *)(0x01b7c100) = *(volatile int *)(0x01b7c100) & 0xfffffffe;
for(i=0;i<4;i++);
*(volatile int *)(0x01b7c100) = *(volatile int *)(0x01b7c100) | 0x08;
*(volatile int *)(0x01b7c114) = 0x08001; // 50MHz/2 = 25MHz
*(volatile int *)(0x01b7c110) = 0x0c; // 25MHz * 12 = 300MHz
*(volatile int *)(0x01b7c118) = 0x08000; // SYSCLK1 = 300MHz/1 = 300MHz
*(volatile int *)(0x01b7c11c) = 0x08001; // SYSCLK2 = 300MHz/2 = 150MHz // Peripheral Clock
*(volatile int *)(0x01b7c120) = 0x08003; // SYSCLK3 = 300MHz/4 = 75MHz // SDRAM Clock
for(i=0;i<4;i++);
*(volatile int *)(0x01b7c100) = *(volatile int *)(0x01b7c100) & 0xfffffff7;
for(i=0;i<4;i++);
*(volatile int *)(0x01b7c100) = *(volatile int *)(0x01b7c100) | 0x01;
}
unsigned short ybr_565(short y,short u,short v)
{
int r,g,b;
b = y + 1772*(u-128)/1000;
if (b<0) b=0;
if (b>255) b=255;
g = y - (344*(u-128) + 714*(v-128))/1000;
if (g<0) g=0;
if (g>255) g=255;
r = y + 1402*(v-128)/1000;
if (r<0) r=0;
if (r>255) r=255;
return ((r&0x0f8)<<8)|((g&0x0fc)<<3)|((b&0x0f8)>>3);
}
void yuyv2yuv(char *yuyv,char *y,char *u,char *v)
{
int i,j,dy,dy1,dy2,s;
for (j=s=dy=dy1=dy2=0;j<240;j++) {
for (i=0;i<320;i+=2) {
u[dy1++] = yuyv[s++];
y[dy++] = yuyv[s++];
v[dy2++] = yuyv[s++];
y[dy++] = yuyv[s++];
}
}
}
interrupt void c_int06(void)
{
if(EDMA_CIPR&0x800){
EDMA_CIPR = 0xffff;
bufsel=(++bufsel&0x01);
Cevent[PaRAM_DST] = (int)cam[(bufsel+1)&0x01];
Levent[PaRAM_SRC] = (int)lcd[(bufsel+1)&0x01];
EDMA_ESR = 0x80;
flag=1;
}
}
void main()
{
int i,j,k,y0,y1,v0,u0;
bufsel = 0;
CSR &= (~0x1);
PLL6713(); // Initialize C6713 PLL
CE0CTL = 0xffffbf33;// SDRAM Space
CE2CTL = (WSU|WST|WHD|RSU|RST|RHD|MTYPE);
SDCTL = 0x57115000;
vm3224init(); // Initialize vm3224k2
vm3224rate(1); // Set frame rate
vm3224bl(15); // Set backlight
VM3224CNTL = VM3224CNTL&0xffff | 0x2; // vm3224 interrupt enable
for (k=0;k<64;k++) // Create RGB565 lookup table
for (i=0;i<32;i++)
for (j=0;j<32;j++) rgb[k][i][j] = ybr_565(k<<2,i<<3,j<<3);
Cevent = (int *)(0x01a00000 + 24 * 7);
Cevent[PaRAM_OPT] = OptionField_0;
Cevent[PaRAM_SRC] = (int)&camcode;
Cevent[PaRAM_CNT] = 1;
Cevent[PaRAM_DST] = (int)&VM3224ADDH;
Cevent = (int *)(0x01a00000 + 24 * 8);
Cevent[PaRAM_OPT] = OptionField_1;
Cevent[PaRAM_SRC] = (int)&VM3224DATA;
Cevent[PaRAM_CNT] = (239<<16)|320;
Cevent[PaRAM_DST] = (int)cam[bufsel];
Cevent[PaRAM_IDX] = 0;
Levent = (int *)(0x01a00000 + 24 * 9);
Levent[PaRAM_OPT] = OptionField_2;
Levent[PaRAM_SRC] = (int)&lcdcode;
Levent[PaRAM_CNT] = 1;
Levent[PaRAM_DST] = (int)&VM3224ADDH;
Levent = (int *)(0x01a00000 + 24 * 10);
Levent[PaRAM_OPT] = OptionField_3;
Levent[PaRAM_SRC] = (int)lcd[bufsel];
Levent[PaRAM_CNT] = (239<<16)|320;
Levent[PaRAM_DST] = (int)&VM3224DATA;
Levent[PaRAM_IDX] = 0;
IER = IER | (1<<6)|3;
CSR = CSR | 0x1;
EDMA_CCER = (1<<8)|(1<<9)|(1<<10);
EDMA_CIER = (1<<11);
EDMA_CIPR = 0xffff;
EDMA_ESR = 0x80;
while (1) {
if(flag) {
// LED = 0;
yuyv2yuv((char *)cam[bufsel],(char *)y,(char *)u,(char *)v);
for(j=0;j<240;j++)
for(i=0;i<320;i++) lcd[bufsel][j][i]=0;
for(j=0;j<240;j+=2)
for(i=0;i<320;i+=2)
out_y[j>>1][i>>1]=(y[j][i]+y[j][i+1]+y[j+1][i]+y[j+1][i+1])>>2;
for(j=0;j<240;j+=2)
for(i=0;i<160;i+=2) {
out_u[j>>1][i>>1]=(u[j][i]+u[j][i+1]+u[j+1][i]+u[j+1][i+1])>>2;
out_v[j>>1][i>>1]=(v[j][i]+v[j][i+1]+v[j+1][i]+v[j+1][i+1])>>2;
}
for (j=0;j<120;j++)
for (i=0;i<160;i+=2) {
y0 = out_y[j][i]>>2;
u0 = out_u[j][i>>1]>>3;
v0 = out_v[j][i>>1]>>3;
y1 = out_y[j][i+1]>>2;
lcd[bufsel][j+60][i+80]=rgb[y0][u0][v0];
lcd[bufsel][j+60][i+81]=rgb[y1][u0][v0];
}
flag=0;
// LED = 1;
}
}
}
