Signals and Variables in VHDL (order) - Problem
- by Morano88
I have a signal and this signal is a bitvector (Z). The length of the bitvector depends on an input n, it is not fixed. In order to find the length, I have to do some computations. Can I define a signal after defining the variables ? It is giving me errors when I do that. It is working fine If I keep the signal before the variables (that what is showing below) .. but I don't want that .. the length of Z depends on the computations of the variables. What is the solution ?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BSD_Full_Comp is
Generic (n:integer:=8);
Port(X, Y : inout std_logic_vector(n-1 downto 0);
FZ : out std_logic_vector(1 downto 0));
end BSD_Full_Comp;
architecture struct of BSD_Full_Comp is
Component BSD_BitComparator
Port ( Ai_1 : inout STD_LOGIC; Ai_0 : inout STD_LOGIC;
Bi_1 : inout STD_LOGIC; Bi_0 : inout STD_LOGIC;
S1 : out STD_LOGIC; S0 : out STD_LOGIC
);
END Component;
Signal Z : std_logic_vector(2*n-3 downto 0);
begin
ass : process
Variable length : integer := n;
Variable pow : integer :=0 ;
Variable ZS : integer :=0;
begin
while length /= 0 loop
length := length/2;
pow := pow+1;
end loop;
length := 2 ** pow;
ZS := length - n;
wait;
end process;
end struct;
