make always rebuild
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by fsdfa
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Published on 2010-04-18T00:27:07Z
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2010/04/18
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My Makefile is:
OBJS = b.o c.o a.o
FLAGS = -Wall -Werror
CC = gcc
test: $(OBJS)
$(CC) $(FLAGS) $(OBJS) -o a
b.o: b.c b.h
$(CC) $(FLAGS) -c b.c
a.o: a.c b.h c.h
$(CC) $(FLAGS) -c a.c
c.o: c.c c.h
$(CC) $(FLAGS) -c c.c
clean:
rm a
rm *.o
all: test
If I do make then make again, it always rebuilds 'test'. Why does it do this?
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