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  • Makefile and rm -f file.{ext1,ext2,ext3} issue

    - by ak91
    Hello, Could you explain me, why Makefile rule: clean: rm -f foo.{bar1,bar2,bar3} does not result in removing files: foo.bar1 foo.bar2 and foo.bar3? I believe I saw pattern like that many times in various Makefiles, but I'm currently writing my own Makefile and can't make that rule work correctly (no files are removed). I'm using: gnu make 3.81 gnu bash 4.1.5 Bash evals that pattern as I suspect: $ echo test.{a,b,c} test.a test.b test.c Thanks!

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  • Make seems to think a prerequisite is an intermediate file, removes it

    - by James
    For starters, this exercise in GNU make was admittedly just that: an exercise rather than a practicality, since a simple bash script would have sufficed. However, it brought up interesting behavior I don't quite understand. I've written a seemingly simple Makefile to handle generation of SSL key/cert pairs as necessary for MySQL. My goal was for make <name> to result in <name>-key.pem, <name>-cert.pem, and any other necessary files (specifically, the CA pair if any of it is missing or needs updating, which leads into another interesting follow-up exercise of handling reverse deps to reissue any certs that had been signed by a missing/updated CA cert). After executing all rules as expected, make seems to be too aggressive at identifying intermediate files for removal; it removes a file I thought would be "safe" since it should have been generated as a prereq to the main rule I'm invoking. (Humbly translated, I likely have misinterpreted make's documented behavior to suit my expectation, but don't understand how. ;-) Edited (thanks, Chris!) Adding %-cert.pem to .PRECIOUS does, of course, prevent the deletion. (I had been using the wrong syntax.) Makefile: OPENSSL = /usr/bin/openssl # Corrected, thanks Chris! .PHONY: clean default: ca clean: rm -I *.pem %: %-key.pem %-cert.pem @# Placeholder (to make this implicit create a rule and not cancel one) Makefile: @# Prevent the catch-all from matching Makefile ca-cert.pem: ca-key.pem $(OPENSSL) req -new -x509 -nodes -days 1000 -key ca-key.pem $@ %-key.pem: $(OPENSSL) genrsa 2048 $@ %-cert.pem: %-csr.pem ca-cert.pem ca-key.pem $(OPENSSL) x509 -req -in $ $@ Output: $ make host1 /usr/bin/openssl genrsa 2048 ca-key.pem /usr/bin/openssl req -new -x509 -nodes -days 1000 -key ca-key.pem ca-cert.pem /usr/bin/openssl genrsa 2048 host1-key.pem /usr/bin/openssl req -new -days 1000 -nodes -key host1-key.pem host1-csr.pem /usr/bin/openssl x509 -req -in host1-csr.pem -days 1000 -CA ca-cert.pem -CAkey ca-key.pem -set_serial 01 host1-cert.pem rm host1-csr.pem host1-cert.pem This is driving me crazy, and I'll happily try any suggestions and post results. If I'm just totally noobing out on this one, feel free to jibe away. You can't possibly hurt my feelings. :)

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  • How to build this project?

    - by Ali Shafai
    Hi, I've been a visual studio developer for long and just trying to understand how things are in linux/unix worl. I found an open source project (Gcomandos) in source forge and tried to build it. when I download the source, I get these files: 16/02/2007 05:16 PM 25,987 aclocal.m4 16/02/2007 05:17 PM 127,445 configure 16/02/2007 05:16 PM 1,925 configure.ac 17/03/2010 03:48 PM <DIR> gComandos 16/02/2007 05:16 PM 332 gcomandos.pc.in 25/11/2006 10:03 PM 9,233 install-sh 16/02/2007 05:16 PM 353 Makefile.am 16/02/2007 05:17 PM 20,662 Makefile.in 16/02/2007 05:16 PM 1,019 Makefile.include 25/11/2006 10:03 PM 11,014 missing I am now lost. I tried making the .am or the .in files, but GnuMake says there is nothing to make. I tried running the shell scripts, but I got errors. Any guidance appreciated.

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  • Recommended build system for latex?

    - by Paul Biggar
    I'm trying to figure out the best build system for latex. Currently, I use latex-makefile, editing in vim, and viewing changes in Okular or gv. The major problem is that it sometimes gets hides errors on me, and I have to run latex manually. The major advantages are that it does all the iteration I need, and offers both pdf and ps simply. If you have experience with latex-mk vim-latex kile lyx miktex latex-makefile the ultimate latex makefile rubber any others I havent come across Would you recommend them, and why/why not?

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  • Mercurial - How to stop tracking modified file but keep the first version in repository.

    - by teerapap
    I create the hg repository with my source tree. I want to keep the first version of some files such as Makefile in the repository and then hg don't see it modified even through I modified it. Original problem is that ./configure usually modifies the Makefile but I don't want the build files to committed in the repository. So I want to keep only first version of configure and Makefile in the repository so that everybody who clone my repository can run ./configure by themself and not bother the repository I tried hg remove or hg forget but those are stop tracking and also delete the files in the next revision of reporitory. .hgignore doesn't do the things too. I think of hg revert everytimes I run ./configure or make but it's not efficient way. Are there any better ways?

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  • Files built with a makefile are disapearing (including the binary)

    - by Reid
    I am building a program on a TS-7800(SBC), and when I run make (show below), it appears to go through all of the steps normally, but in the end i do not get a binary file. Why is this, and how can I get my file. makefile CC= /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc # compiler options #CFLAGS= -O2 CFLAGS= -mcpu=arm9 #CFLAGS= -pg -Wall # linker LN= $(CC) # linker options LNFLAGS= #LNFLAGS= -pg # extra libraries used in linking (use -l command) LDLIBS= -lpthread # source files SOURCES= HMITelem.c Cpacket.c GPS.c ADC.c Wireless.c Receivers.c CSVReader.c RPM.c RS485.c # include files INCLUDES= Cpacket.h HMITelem.h CSVReader.h RS485.h # object files OBJECTS= HMITelem.o Cpacket.o GPS.o ADC.o Wireless.o Receivers.o CSVReader.o RPM.o RS485.o HMITelem: $(OBJECTS) $(LN) $(LNFLAGS) -o $@ $(OBJECTS) $(LDLIBS) .c.o: $*.c $(CC) $(CFLAGS) -c $*.c RUN : ./HMITelem #clean: # rm -f *.o # rm -f *~ Output root@ts7800:ReidTest# make /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c HMITelem.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c Cpacket.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c GPS.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c ADC.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c Wireless.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c Receivers.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c CSVReader.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c RPM.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -mcpu=arm9 -c RS485.c /home/eclipse/ReidTest/cc/cross-toolchains/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-gcc -o HMITelem HMITelem.o Cpacket.o GPS.o ADC.o Wireless.o Receivers.o CSVReader.o RPM.o RS485.o -lpthread Thank you.

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  • How to use make and compile as C99?

    - by djTeller
    I'm trying to compile a linux kernel module using a Makefile: obj-m += main.o all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean Which gives me: main.c:54: warning: ISO C90 forbids mixed declarations and code I need to switch to C99. After reading I noticed I need to add a flag -std=c99, not sure where it suppose to be added. How do I change the Makefile so it will compile as C99?

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  • MakeFiles and dependancies

    - by Michael
    Hello, I'm writing a makefile and I can't figure out how to include all my source files without having to write all source file I want to use. Here is the makefile I'm currently using: GCC= $(GNUARM_HOME)\bin\arm-elf-gcc.exe SOURCES=ShapeApp.cpp Square.cpp Circle.cpp Shape.cpp OBJECTS=$(SOURCES:.cpp=.o) EXECUTABLE=hello all: $(EXECUTABLE) $(EXECUTABLE): $(OBJECTS) #$(CC) $(LDFLAGS) $(OBJECTS) -o $@ .cpp.o: $(GCC) -c $< -o $@ How do I automatically add new source file without having to add it to the sources line? Thanks, Mike.

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  • MakeFiles and dependencies

    - by Michael
    Hello, I'm writing a makefile and I can't figure out how to include all my source files without having to write all source file I want to use. Here is the makefile I'm currently using: GCC = $(GNUARM_HOME)\bin\arm-elf-gcc.exe SOURCES=ShapeApp.cpp Square.cpp Circle.cpp Shape.cpp OBJECTS=$(SOURCES:.cpp=.o) EXECUTABLE=hello all: $(EXECUTABLE) $(EXECUTABLE): $(OBJECTS) #$(CC) $(LDFLAGS) $(OBJECTS) -o $@ .cpp.o: $(GCC) -c $< -o $@ How do I automatically add new source file without having to add it to the sources line?

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  • Trouble creating a makefile

    - by catia
    Hi everyone! I'm having some trouble making a Makefile. Write now I just compile everything every time. Although, the professor is ok with that, I do want to get it working faster and to avoid unnecessary compiling. Here's what I have. FILES= p6.cpp SetIter.cpp Node.cpp Set.cpp CFLAGS= -ansi -pendantic -Wall -Wextra CC= g++ MakePg6: p6.cpp SetIter.cpp Node.cpp Set.cpp $(CC) $(CFLAGS) $(FILES) -o pg6 Node.cpp - node class Set.cpp - uses nodes. Friend of Node. SetIter.cpp - gets a set and uses a pointer to iterator through I'm confused with some of the depencies arising from the friends thing and the point of lib.o being included in the Makefile as some sites have. Any help is greatly appreciated. Thanks in advance.

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  • Setting Environment Variables For NMAKE Before Building A 'Makefile Solution'

    - by John Dibling
    I have an MSVC Makefile Project in which I need to set an environment variable before running NMAKE. For x64 builds I needs to set it to one value, and for x86 builds I need to set it to something else. So for example, when doing a build I would want to SET PLATFORM=win64 if I'm building a 64-bit compile, or SET PLATFORM=win32 if I'm building 32-bit. There does not appear to be an option to set environment variables or add a pre-build even for makefile projects. How do I do this? EDIT: Running MSVC 2008

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  • Replacing the end of the line by SED in makefile

    - by Masi
    How can you append to the end of a line by SED controlled by makefile? I run paste -d" " t.tex tE.tex | sed 's@$@XXX@' > tM.tex where the problem is in the use of the mark $ for the end of the line. I get #paste -d" " t.tex tE.tex | sed -e s/" "/\\\&/g | sed -r "s/XXX/" > tM.tex sed: -e expression #1, char 10: unterminated `s' command make: *** [all] Error 1 I have the command just after the "all:" tag in my makefile which contains only the two lines. The parameters -n and -e do not help here. The command works as expected run when it is run directly in terminal.

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  • wired connection not working in ubuntu 12.04 on lenovo G580 laptop

    - by shravankumar
    I found solution in http://www.zyxware.com/articles/2680/solved-wired-connection-eth0-not-detected-in-ubuntu-12-04 I downloaded compact-wireless-2012-07-03-p.tar.bz2 Here the steps i followed along with output 1. shravankumar@shravankumar-Lenovo-G580:~/Desktop/compat-wireless-2012-07-03-p$ scripts/driver-select alx Output: Processing new driver-select request... Backup exists: Makefile.bk Backup exists: Makefile.bk Backup exists: drivers/net/ethernet/broadcom/Makefile.bk Backup exists: drivers/net/ethernet/atheros/Makefile.bk Backup exists: Makefile.bk Backup exists: Makefile.bk Backup exists: drivers/net/ethernet/broadcom/Makefile.bk 2.shravankumar@shravankumar-Lenovo-G580:~/Desktop/compat-wireless-2012-07-03-p$ make output: make -C /lib/modules/3.2.0-23-generic/build M=/home/shravankumar/Desktop/compat-wireless-2012-07-03-p modules make[1]: Entering directory `/usr/src/linux-headers-3.2.0-23-generic' scripts/Makefile.build:44: /home/shravankumar/Desktop/compat-wireless-2012-07-03-p/drivers/net/ethernet/atheros/alx/Makefile: No such file or directory make[4]: *** No rule to make target `/home/shravankumar/Desktop/compat-wireless-2012-07-03-p/drivers/net/ethernet/atheros/alx/Makefile'. Stop. make[3]: *** [/home/shravankumar/Desktop/compat-wireless-2012-07-03-p/drivers/net/ethernet/atheros/alx] Error 2 make[2]: *** [/home/shravankumar/Desktop/compat-wireless-2012-07-03-p/drivers/net/ethernet/atheros] Error 2 make[1]: *** [_module_/home/shravankumar/Desktop/compat-wireless-2012-07-03-p] Error 2 make[1]: Leaving directory `/usr/src/linux-headers-3.2.0-23-generic' make: *** [modules] Error 2 3. hravankumar@shravankumar-Lenovo-G580:~/Desktop/compat-wireless-2012-07-03-p$ make install output: FATAL: Could not open /lib/modules/3.2.0-23-generic/modules.dep.temp for writing: Permission denied make: *** [uninstall] Error 1 4. shravankumar@shravankumar-Lenovo-G580:~/Desktop/compat-wireless-2012-07-03-p$ modeprobe alx output: No command 'modeprobe' found, did you mean: Command 'modprobe' from package 'module-init-tools' (main) modeprobe: command not found I am new to Ubuntu ,Please help me. Thanks in advance

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  • Makefiles - Compile all .cpp files in src/ to .o's in obj/, then link to binary in /

    - by Austin Hyde
    So, my project directory looks like this: /project Makefile main /src main.cpp foo.cpp foo.h bar.cpp bar.h /obj main.o foo.o bar.o What I would like my makefile to do would be to compile all .cpp files in the /src folder to .o files in the /obj folder, then link all the .o files in /obj into the output binary in the root folder /project. The problem is, I have next to no experience with Makefiles, and am not really sure what to search for to accomplish this. Also, is this a "good" way to do this, or is there a more standard approach to what I'm trying to do?

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  • How can I handle template dependencies in Template Toolkit?

    - by Smack my batch up
    My static web pages are built from a huge bunch of templates which are inter-included using Template Toolkit's "import" and "include", so page.html looks like this: [% INCLUDE top %] [% IMPORT middle %] Then top might have even more files included. I have very many of these files, and they have to be run through to create the web pages in various languages (English, French, etc., not computer languages). This is a very complicated process and when one file is updated I would like to be able to automatically remake only the necessary files, using a makefile or something similar. Are there any tools like makedepend for C files which can parse template toolkit templates and create a dependency list for use in a makefile? Or are there better ways to automate this process?

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  • perl ENV value avoid escape

    - by Michael
    In my makefile I have command in variable like this substitute := perl -p -e 's/@([^@]+)@/"$(update_url)"/ge' > output.txt update_url := em:updateURL=\"http:\/\/bla\/update.rdf\"\n this works fine when I run command in target and I have newline, quotes however I need to replace $(update_url)" with environment variable, using expression like this #substitute := perl -p -e 's/@([^@]+)@/defined $$ENV{$$1} ? $$ENV{$$1} : $$1/ge' I am exporting those variables from makefile. This gives me literally em:updateURL=\"http:\/\/bla\/update.rdf\"\n on output file... so how to make the second version to give output like first version?

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  • why make said no rule to make target

    - by guilin ??
    Isn't Makefile syntax is target: require_files cmd... Why I got this problem? Makefile MXMLC = /opt/flex/bin/mxmlc MXMLC_RELEASE = $(MXMLC) -debug=false -compiler.optimize=true release: bin-release/Wrapper.swf, bin-release/Application.swf bin-release/Application.swf: src/**/*.as, lib/*.swc $(MXMLC_RELEASE) -output bin-release/Application.swf src/Application.as @@-rm ../server/public/game/Application.swf $(CP) bin-release/Application.swf ../server/public/game/Application.swf bin-release/Wrapper.swf: src/*.as, src/engine/**/*.as, lib/*.swc $(MXMLC_RELEASE) -output bin-release/Wrapper.swf src/Wrapper.as @@-rm ../server/public/game/Wrapper.swf $(CP) bin-release/Wrapper.swf ../server/public/game/Wrapper.swf $: make bin-release/Application.swf ~/workspace/project/src/flash [2]19:20 make: * No rule to make target src/constant/*.as,', needed bybin-release/Application.swf'. Stop.

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  • Re-execute target when specified as dependency to multiple rules

    - by andrew
    I have the following GNU makefile: .PHONY a b c d a: b c b: d c: d d: echo HI I would like the target 'd' to be run twice -- since it is specified as a dependency by both b & c. Unfortunately, the target 'd' will be executed only once. The output of running make will simply be 'HI', instead of 'HI HI'. How can I fix this? Thanks! To Clarify, the goal is something like this: subdirs = a b c build: x y x: target=build x: $(subdirs) y: target=prepare y: $(subdirs) $(subdirs): $(make) -f $@/makefile $(target)

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  • What is this project/compilation source structure?

    - by Werner
    Hi, I am working on some project my boss sent to me. After unzipping, this is the structure of the files: executable_file config.mk doc include lib Makefile sources I have only worked with "usual" Makefile projects. But I do not undersatnd the meaning of config.mk here. Do you know which kind of "build" structure (what is the right name for this concept?) is it, and where can i find more information about this? I need to modify it, so it compiles in another hardware, so I do not know where I sohuld work on. Thanks

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  • Run Iphone app in simulator from the terminal : how to set up iPhoneSim ?

    - by user142764
    Hi, I found this project which seems to make it possible to run an iPhone app from command line ! http://github.com/jhaynie/iphonesim Unfortunately there is almost no documentation and i'm stuck at building this project : I download all sources I run MakeFile and i get these errors : admin$ ./Makefile ./Makefile: line 4: -Werror: command not found ./Makefile: line 5: AppKit: command not found ./Makefile: line 6: Source/main.o: No such file or directory ./Makefile: line 11: .SUFFIXES:: command not found ./Makefile: line 12: .m.o:: command not found ./Makefile: line 13: -o: No such file or directory ./Makefile: line 15: all:: command not found ./Makefile: line 17: iphonesim:: command not found gcc-4.2: argument to '-o' is missing ./Makefile: line 20: clean:: command not found As anybody been able to build and use this project ? Thanks, Vincent

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  • variable=@value@ in Makefiles

    - by user1447110
    I understand that @ suppresses printing of a command in a Makefile... http://www.gnu.org/software/make/manual/make.html#Echoing ... and I understand that $@ is the target name... http://www.gnu.org/software/make/manual/make.html#Automatic-Variables ... but I can't find any information on what a line like this might mean: variable=@value@ I'm not trying to fix anything here, just trying to better understand Makefiles. Update: The "Makefile Subsitutions" section of the GNU autoconf manual explains that it's a value that is substituted by autoconf.

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