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  • Denormalization Strategies

    In building a database, typically we want a well normalized design. However there are cases for considering options for denormalization in complex systems. Timothy Claason gives you some thoughts on the subject.

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  • Searching for entity awareness in 3D space algorithm and data structure

    - by Khanser
    I'm trying to do some huge AI system just for the fun and I've come to this problem. How can I let the AI entities know about each other without getting the CPU to perform redundant and costly work? Every entity has a spatial awareness zone and it has to know what's inside when it has to decide what to do. First thoughts, for every entity test if the other entities are inside the first's reach. Ok, so it was the first try and yep, that is redundant and costly. We are working with real time AI over 10000+ entities so this is not a solution. Second try, calculate some grid over the awareness zone of every entity and test whether in this zones are entities (we are working with 3D entities with float x,y,z location coordinates) testing every point in the grid with the indexed-by-coordinate entities. Well, I don't like this because is also costly, but not as the first one. Third, create some multi linked lists over the x's and y's indexed positions of the entities so when we search for an interval between x,y and z,w positions (this interval defines the square over the spatial awareness zone) over the multi linked list, we won't have 'voids'. This has the problem of finding the nearest proximity value if there isn't one at the position where we start the search. I'm not convinced with any of the ideas so I'm searching for some enlightening. Do you people have any better ideas?

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  • Is there a constraint-based scheduling/calendar application?

    - by wonsungi
    Is there a constraint-based scheduling/calendar application? This application would be used to coordinate multiple people's schedules. Two basic use cases: Multiple people need to schedule a time to meet together. Everyone is busy at different days/times. Each person enters blocks of days/times they cannot meet, and the application suggests the best times to meet given a desired time range. Multiple people need to use some common resources for a specific length of time (over some time span like a week), but the exact date/time does not matter. These people enter the resources and time needed, and the application suggests the best way to share these resources. This use case still accounts for people's blocks of busy time. I imagine this program would be graphical, but other interfaces would be acceptable. Also preferable if web-based/works on both PC's and Mac's, but PC-only/Mac-only solutions are acceptable.

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  • Much ado about NULL: Exploiting a kernel NULL dereference

    <b>Ksplice:</b> "We think that it&#8217;s important for developers and system administrators to be more knowledgeable about the attacks that black hats regularly use to take control of systems, and so, today, we&#8217;re going to start from where we left off and go all the way to a working exploit for a NULL pointer dereference in a toy kernel module."

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  • Application Virtualization has challenges

    - by llaszews
    information Week article discusses the challenges associated virtualizing applications in the cloud: Application Virtualization Challenges 'Golden images' quickly diverge from their pristine initial condition because of: 1. OS patches 2. Application updates 3. Configuration changes "Applications, once released into the wild, tend to quickly diverge from the golden image" "The difficulties face by developers and systems admins in deploying apps to the cloud are reminiscent of those encountered transitioning from mainframe to the client/server era"

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  • USB mouse pointer only moving horizontally on macbook 6.2 with 12.04

    - by Glyn Normington
    After installing Ubuntu 12.04 on a macbook pro 6.2, the touchpad and external USB mouse worked perfectly. After rebooting I can't get either touchpad or external USB mouse to work. Sometimes no mouse pointer is visible, but more often I can only move the mouse pointer horizontally five sixths of the way across the display (from the top left). I have uninstalled mouseemu. xinput list shows the USB mouse. xinput query-state for the USB mouse shows the following: ButtonClass button[1]=up ... button[16]=up ValuatorClass Mode=Relative Proximity=In valuator[0]=480 valuator[1]=2400 valuator[2]=0 valuator[3]=3 and re-issuing this command with the pointer at its right hand extreme displays the same except for: valuator[0]=1679 So the valuator[0] seems to be the x-coordinate of the pointer and the range of motion 480-1679 is indeed about five sixths of the display width (1440). valuator[1] is suspiciously large given the display height is 900. Perhaps this is a side-effect of having previously been using a dual monitor (although booting with that monitor connected does not help). There are other entries listed under xinput list: Virtual core XTEST pointer which seems stuck at position (840,1050). bcm5974 which seems stuck at position (837,6700). Removing the bcm5974 module using rmmod disables the toucpad as expected but does not fix the USB mouse problem. After adding the module back, it is stuck at position (840,1050) instead of (837,6700). /etc/X11/xorg.conf was generated by nvidia-settings and contains: Section "InputDevice" # generated from default Identifier "Mouse0" Driver "mouse" Option "Protocol" "auto" Option "Device" "/dev/psaux" Option "ZAxisMapping" "4 5" although I don't know how plausible these settings are. Any suggestions?

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  • XSIGO Product Training Now Available

    - by Cinzia Mascanzoni
    Xsigo Sales and Pre-Sales training is available via iLearning for partners registered in OPN Server and Storage Systems Knowledge Zones. The recommended online training sessions provide sales training solutions that equip partners with the product knowledge, market knowledge and selling strategies to help achieve their revenue targets. Partners are invited to learn more here: Sales Training: Product Essentials For Sales - Oracle Virtual Networking Pre-Sales Training and Product Essentials For Sales Consultants - Oracle Virtual Networking.

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  • help configuring my samba file server

    - by user281745
    Hello everyone I have installed all the files I needed for my samba file server. I have also installed the gadmin-samba 0.3.2. I am trying to set a user-name and password also I would like to know how to ad my laptops I own to the machines allowed to connect to it. it can be in terminal but preferably in gadmin-samba which is like a GUI. please be very descriptive my systems is Ubuntu 14.04 and Gadmin-Samba 0.3.2

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  • Organization &amp; Architecture UNISA Studies &ndash; Chap 4

    - by MarkPearl
    Learning Outcomes Explain the characteristics of memory systems Describe the memory hierarchy Discuss cache memory principles Discuss issues relevant to cache design Describe the cache organization of the Pentium Computer Memory Systems There are key characteristics of memory… Location – internal or external Capacity – expressed in terms of bytes Unit of Transfer – the number of bits read out of or written into memory at a time Access Method – sequential, direct, random or associative From a users perspective the two most important characteristics of memory are… Capacity Performance – access time, memory cycle time, transfer rate The trade off for memory happens along three axis… Faster access time, greater cost per bit Greater capacity, smaller cost per bit Greater capacity, slower access time This leads to people using a tiered approach in their use of memory   As one goes down the hierarchy, the following occurs… Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access of the memory by the processor The use of two levels of memory to reduce average access time works in principle, but only if conditions 1 to 4 apply. A variety of technologies exist that allow us to accomplish this. Thus it is possible to organize data across the hierarchy such that the percentage of accesses to each successively lower level is substantially less than that of the level above. A portion of main memory can be used as a buffer to hold data temporarily that is to be read out to disk. This is sometimes referred to as a disk cache and improves performance in two ways… Disk writes are clustered. Instead of many small transfers of data, we have a few large transfers of data. This improves disk performance and minimizes processor involvement. Some data designed for write-out may be referenced by a program before the next dump to disk. In that case the data is retrieved rapidly from the software cache rather than slowly from disk. Cache Memory Principles Cache memory is substantially faster than main memory. A caching system works as follows.. When a processor attempts to read a word of memory, a check is made to see if this in in cache memory… If it is, the data is supplied, If it is not in the cache, a block of main memory, consisting of a fixed number of words is loaded to the cache. Because of the phenomenon of locality of references, when a block of data is fetched into the cache, it is likely that there will be future references to that same memory location or to other words in the block. Elements of Cache Design While there are a large number of cache implementations, there are a few basic design elements that serve to classify and differentiate cache architectures… Cache Addresses Cache Size Mapping Function Replacement Algorithm Write Policy Line Size Number of Caches Cache Addresses Almost all non-embedded processors support virtual memory. Virtual memory in essence allows a program to address memory from a logical point of view without needing to worry about the amount of physical memory available. When virtual addresses are used the designer may choose to place the cache between the MMU (memory management unit) and the processor or between the MMU and main memory. The disadvantage of virtual memory is that most virtual memory systems supply each application with the same virtual memory address space (each application sees virtual memory starting at memory address 0), which means the cache memory must be completely flushed with each application context switch or extra bits must be added to each line of the cache to identify which virtual address space the address refers to. Cache Size We would like the size of the cache to be small enough so that the overall average cost per bit is close to that of main memory alone and large enough so that the overall average access time is close to that of the cache alone. Also, larger caches are slightly slower than smaller ones. Mapping Function Because there are fewer cache lines than main memory blocks, an algorithm is needed for mapping main memory blocks into cache lines. The choice of mapping function dictates how the cache is organized. Three techniques can be used… Direct – simplest technique, maps each block of main memory into only one possible cache line Associative – Each main memory block to be loaded into any line of the cache Set Associative – exhibits the strengths of both the direct and associative approaches while reducing their disadvantages For detailed explanations of each approach – read the text book (page 148 – 154) Replacement Algorithm For associative and set associating mapping a replacement algorithm is needed to determine which of the existing blocks in the cache must be replaced by a new block. There are four common approaches… LRU (Least recently used) FIFO (First in first out) LFU (Least frequently used) Random selection Write Policy When a block resident in the cache is to be replaced, there are two cases to consider If no writes to that block have happened in the cache – discard it If a write has occurred, a process needs to be initiated where the changes in the cache are propagated back to the main memory. There are several approaches to achieve this including… Write Through – all writes to the cache are done to the main memory as well at the point of the change Write Back – when a block is replaced, all dirty bits are written back to main memory The problem is complicated when we have multiple caches, there are techniques to accommodate for this but I have not summarized them. Line Size When a block of data is retrieved and placed in the cache, not only the desired word but also some number of adjacent words are retrieved. As the block size increases from very small to larger sizes, the hit ratio will at first increase because of the principle of locality, which states that the data in the vicinity of a referenced word are likely to be referenced in the near future. As the block size increases, more useful data are brought into cache. The hit ratio will begin to decrease as the block becomes even bigger and the probability of using the newly fetched information becomes less than the probability of using the newly fetched information that has to be replaced. Two specific effects come into play… Larger blocks reduce the number of blocks that fit into a cache. Because each block fetch overwrites older cache contents, a small number of blocks results in data being overwritten shortly after they are fetched. As a block becomes larger, each additional word is farther from the requested word and therefore less likely to be needed in the near future. The relationship between block size and hit ratio is complex, and no set approach is judged to be the best in all circumstances.   Pentium 4 and ARM cache organizations The processor core consists of four major components: Fetch/decode unit – fetches program instruction in order from the L2 cache, decodes these into a series of micro-operations, and stores the results in the L2 instruction cache Out-of-order execution logic – Schedules execution of the micro-operations subject to data dependencies and resource availability – thus micro-operations may be scheduled for execution in a different order than they were fetched from the instruction stream. As time permits, this unit schedules speculative execution of micro-operations that may be required in the future Execution units – These units execute micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers Memory subsystem – This unit includes the L2 and L3 caches and the system bus, which is used to access main memory when the L1 and L2 caches have a cache miss and to access the system I/O resources

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  • Oracle OpenWorld 2012 konferencia 9 nap múlva kezdodik, 09.30.-10.04.

    - by user645740
    San Franciscoban nemsokára elkezdodik a 2012. évi Oracle OpenWorld konferencia:http://www.oracle.com/openworld/. Rengeteg érdekes keynote, eloadás, demó, stb található a programban. Oracle OpenWorld keynote eloadások: http://www.oracle.com/openworld/keynotes/ Az Oracle OpenWorld-ön gyakran fontos bejelentések is elhangzanak, kíváncsian várom az idei újdonságokat! Továbbra is kulcsszavak: Cloud - felho Hardware and Software, Engineered to Work Together Engineered Systems A komplexitás csökkentése Business Analytics (üzleti intelligencia és barátai nagyobb keretben) Fusion Applications

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  • unable to boot and boot-loop on splash screen

    - by Joel St Martin
    hey i have tried to install ubuntu many times, but once it installs it boot-loops at the splash screen. it just loops through the boot sound and the screen not sure why. nothing has seemed to work. also its only alowing me to boot windows all other oporating systems crash and loop just like ubuntu (android x86, linux mint, red hat, ubuntustudio). compac amd 64 3400+ 1gig ram 2 hhd (200 gig/120 gig) 1 ssd (500gig) win7 x86 a video showing what happens

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  • Thoughts on type aliases/synonyms?

    - by Rei Miyasaka
    I'm going to try my best to frame this question in a way that doesn't result in a language war or list, because I think there could be a good, technical answer to this question. Different languages support type aliases to varying degrees. C# allows type aliases to be declared at the beginning of each code file, and they're valid only throughout that file. Languages like ML/Haskell use type aliases probably as much as they use type definitions. C/C++ are sort of a Wild West, with typedef and #define often being used seemingly interchangeably to alias types. The upsides of type aliasing don't invoke too much dispute: It makes it convenient to define composite types that are described naturally by the language, e.g. type Coordinate = float * float or type String = [Char]. Long names can be shortened: using DSBA = System.Diagnostics.DebuggerStepBoundaryAttribute. In languages like ML or Haskell, where function parameters often don't have names, type aliases provide a semblance of self-documentation. The downside is a bit more iffy: aliases can proliferate, making it difficult to read and understand code or to learn a platform. The Win32 API is a good example, with its DWORD = int and its HINSTANCE = HANDLE = void* and its LPHANDLE = HANDLE FAR* and such. In all of these cases it hardly makes any sense to distinguish between a HANDLE and a void pointer or a DWORD and an integer etc.. Setting aside the philosophical debate of whether a king should give complete freedom to their subjects and let them be responsible for themselves or whether they should have all of their questionable actions intervened, could there be a happy medium that would allow the benefits of type aliasing while mitigating the risk of its abuse? As an example, the issue of long names can be solved by good autocomplete features. Visual Studio 2010 for instance will alllow you to type DSBA in order to refer Intellisense to System.Diagnostics.DebuggerStepBoundaryAttribute. Could there be other features that would provide the other benefits of type aliasing more safely?

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  • RoboForm Enterprise v7 Reviewed

    With an established pedigree in the consumer market, RoboForm is making the move to the enterprise with some good and bad results. eSecurityPlanet's thorough review says Siber Systems has delivered enough to warrant business consideration.

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  • RoboForm Enterprise v7 Reviewed

    With an established pedigree in the consumer market, RoboForm is making the move to the enterprise with some good and bad results. eSecurityPlanet's thorough review says Siber Systems has delivered enough to warrant business consideration.

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  • Les risques du Cloud sont plus importants que ses avantages, pour les responsables IT interrogés par

    Mise à jour du 08/04/10 [Les commentaires sur cette mise à jour commencent ici] Les risques du Cloud Computing sont plus grands que ses avantages Pour les responsables IT interrogés par l'ISACA Près de la moitié (45%) des responsables IT interrogés dans une étude de l'ISACA (la Information Systems Audit and Control Association) considèrent que les risques liés au Cloud Computing sont plus importants que ses avantages, 38% pensent que risques et bénéfices s'équilibrent, et seulement 12% pensent que...

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  • Could not display chart. The control is not properly registered. (4 replies)

    I've seen other people raise this in searching the web but can't find any definitive answers so apologies if this has been answered previously (but please point me in that direction). I have two XP Pro SP2 workstations one works fine in that it shows the result graphs in ACT (v1.0.536.0) and the other gives the error &quot;Could not display chart. The control is not properly registered.&quot;. Both systems ...

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  • Improve Microsoft Visual C++ Application Security and Robustness with SafeInt

    In this age of cloud computing, massive parallel systems and complex security threats like identity theft and decentralized botnets, devoting resources to combat the seemingly age-old issue of integer overflow appears distinctly passC). Despite the fact that integer overflow is such a well know problem, particularly within C and C++ programming, the problem remains a real issue from both a defect and security standpoint, that's why the introduction of the SafeInt template class in Visual C++ 2010 to address overflows is a great addition.

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  • Bricscad V12 on ubuntu 11.10!

    - by gabriel
    i tried to install bricscad from the deb file but is for 32bit systems.So i had problems and i downloaded the .tgz file and ran tar -xvf and i was in the directory /opt/bricsys/bricscad/v12 So i managed to run bricscad with the command sudo sh bricscad.sh in the directory this.So my question is, do you have any idea of how to make a launcher or smthing so i can run the program from an easier way?I cannot find it in dash(unity) or in the desktop. Any help will be great! Thanks

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  • HTML5 Canvas Converting between cartesian and isometric coordinates

    - by Amir
    I'm having issues wrapping my head around the Cartesian to Isometric coordinate conversion in HTML5 canvas. As I understand it, the process is two fold: (1) Scale down the y-axis by 0.5, i.e. ctx.scale(1,0.5); or ctx.setTransform(1,0,0,0.5,0,0); This supposedly produces the following matrix: [x; y] x [1, 0; 0, 0.5] (2) Rotate the context by 45 degrees, i.e. ctx.rotate(Math.PI/4); This should produce the following matrix: [x; y] x [cos(45), -sin(45); sin(45), cos(45)] This (somehow) results in the final matrix of ctx.setTransform(2,-1,1,0.5,0,0); which I cannot seem to understand... How is this matrix derived? I cannot seem to produce this matrix by multiplying the scaling and rotation matrices produced earlier... Also, if I write out the equation for the final transformation matrix, I get: newX = 2x + y newY = -x + y/2 But this doesn't seem to be correct. For example, the following code draws an isometric tile at cartesian coordinates (500, 100). ctx.setTransform(2,-1,1,0.5,0,0); ctx.fillRect(500, 100, width*2, height); When I check the result on the screen, the actual coordinates are (285, 215) which do not satisfy the equations I produced earlier... So what is going on here? I would be very grateful if you could: (1) Help me understand how the final isometric transformation matrix is derived; (2) Help me produce the correct equation for finding the on-screen coordinates of an isometric projection. Many thanks and kind regards

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