Posted
by EquinoX
on Stack Overflow
See other posts from Stack Overflow
or by EquinoX
Published on 2010-04-21T23:14:08Z
Indexed on
2010/04/22
0:13 UTC
Read the original article
Hit count: 614
I am getting the warning that:
One or more signals are missing in the sensitivity list of always block.
always@(Address)begin
ReadData = instructMem[Address];
end
How do I get rid of this warning?
© Stack Overflow or respective owner
as seen on Stack Overflow
- Search for 'Stack Overflow'
Hi,
When programming in VHDL, can you use a variable in a case statement? This variable will modified by one of the cases
i.e.
case task is
when 1 =>
when 2 =>
when number =>
is this OK?
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
I am getting the warning that:
One or more signals are missing in the sensitivity list of always block.
always@(Address)begin
ReadData = instructMem[Address];
end
How do I get rid of this warning?
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
I have pex_pkg.vhd and I want to use this library to make floating point adder but altera max+plus II give me an error can't open "PEX_lib" how to include this library in max+plus ?
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
Hey,
Quick VHDL question, I don't have access to Xilinx at the moment due to dead laptop, so can't test this.
I was wondering if it's possible to use variables and arithmetic in 'downto' statements, e.g:
proc: process (x)
begin
y <= z(x downto 0) & z(7 downto x);
end process;
Thanks.
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
Hi, i'm coding a 4-bit binary adder with accumulator:
library ieee;
use ieee.std_logic_1164.all;
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:inout bit;
done:out bit);
end binadder;
architecture binadder of binadder is
signal state:…
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
how to create a connection in verilog which interconnects a,b,c,d where a,b,c are inputs.?
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
I am doing a project in Verilog, and the project is a low power parallel multiplier. I am going to fed the codings in FPGA kit. I need model Veriog codings. In which site can I get or suggest some good books.
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
for (j=0;j<k;j=j+1) begin:loop2
assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]};
end
row is a register.
It does not work as I am doing it. Can anyone please help me to fix it?
Thank you very much.
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
for (j=0;j<k;j=j+1) begin:loop2
assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]};
end
row is a register,
it does not work as I am doing it. Can anyone please help me to fix it?
Thank you very much.
>>> More
as seen on Stack Overflow
- Search for 'Stack Overflow'
I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly?
http://pastebin…
>>> More
