Case statements in VHDL
Posted
by cheryl
on Stack Overflow
See other posts from Stack Overflow
or by cheryl
Published on 2010-04-08T02:51:13Z
Indexed on
2010/04/08
3:13 UTC
Read the original article
Hit count: 673
Hi,
When programming in VHDL, can you use a variable in a case statement? This variable will modified by one of the cases
i.e.
case task is
when 1 =>
when 2 =>
when number =>
is this OK?
© Stack Overflow or respective owner