Case statements in VHDL

Posted by cheryl on Stack Overflow See other posts from Stack Overflow or by cheryl
Published on 2010-04-08T02:51:13Z Indexed on 2010/04/08 3:13 UTC
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Hi,

When programming in VHDL, can you use a variable in a case statement? This variable will modified by one of the cases

i.e.

case task is

when 1 =>

when 2 => 

when number =>

is this OK?

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