Exporting tasks to 'C using DPI

Posted by Alphaneo on Stack Overflow See other posts from Stack Overflow or by Alphaneo
Published on 2009-04-07T07:22:40Z Indexed on 2010/05/15 1:44 UTC
Read the original article Hit count: 427

Filed under:

verilog

|

system-verilog

|

DPI

|

Hardware

|

verification

I have an verilog based test-bench, interfaced to 'C source using DPI. Now using DPI I am planning to write my whole firmware. To do this I need 3 things

Register Read
Register Write
Interrupt handler As I understand, register reads and writes are tasks that I need to export from the RTL test-bench. And Interrupt handler (I implemented by importing a function from 'C).

I checked most the cadence documentation and found no useful hints. I have also registered with cadence users community but it seems that I cannot ask question till they approve my registration.

Just in case someone is aware of this, would appreciate their help.

© Stack Overflow or respective owner

Related posts about verilog

multiple input wire definiton in verilog?

as seen on Stack Overflow - Search for 'Stack Overflow'
how to create a connection in verilog which interconnects a,b,c,d where a,b,c are inputs.? >>> More
Where can i get Verilog codings?

as seen on Stack Overflow - Search for 'Stack Overflow'
I am doing a project in Verilog, and the project is a low power parallel multiplier. I am going to fed the codings in FPGA kit. I need model Veriog codings. In which site can I get or suggest some good books. >>> More
Assign a value to a reg in Verilog

as seen on Stack Overflow - Search for 'Stack Overflow'
for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register. It does not work as I am doing it. Can anyone please help me to fix it? Thank you very much. >>> More
assign a value to reg in verilog

as seen on Stack Overflow - Search for 'Stack Overflow'
for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register, it does not work as I am doing it. Can anyone please help me to fix it? Thank you very much. >>> More
Verilog code simulates but does not run as predicted on FPGA

as seen on Stack Overflow - Search for 'Stack Overflow'
I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin… >>> More

Related posts about system-verilog

How to change the probability distribution of SystemVerilog random variables?

as seen on Stack Overflow - Search for 'Stack Overflow'
This is for SystemVerilog. I know you can specify weights for values, or ranges of values, in the set of values that a random variable chooses from, but what if you want a nice Gaussian distribution? How do you write that kind of constraint? >>> More
verilog / systemverilog -- What is the behavior of blocking statements across two always blocks?

as seen on Stack Overflow - Search for 'Stack Overflow'
I am wondering about the behavior of the below code. There are two always blocks, one is combinational to calculate the next_state signal, the other is sequential which will perform some logic and determine whether or not to shutdown the system. It does this by setting the shutdown_now signal high… >>> More
Assign a value to a reg in Verilog

as seen on Stack Overflow - Search for 'Stack Overflow'
for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register. It does not work as I am doing it. Can anyone please help me to fix it? Thank you very much. >>> More
assign a value to reg in verilog

as seen on Stack Overflow - Search for 'Stack Overflow'
for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register, it does not work as I am doing it. Can anyone please help me to fix it? Thank you very much. >>> More
Exporting tasks to 'C using DPI

as seen on Stack Overflow - Search for 'Stack Overflow'
I have an verilog based test-bench, interfaced to 'C source using DPI. Now using DPI I am planning to write my whole firmware. To do this I need 3 things Register Read Register Write Interrupt handler As I understand, register reads and writes are tasks that I need to export from the RTL test-bench… >>> More