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  • Design Pattern Advice for Bluetooth App for Android

    - by Aimee Jones
    I’m looking for some advice on which patterns would apply to some of my work. I’m planning on doing a project as part of my college work and I need a bit of help. My main project is to make a basic Android bluetooth tracking system where the fixed locations of bluetooth dongles are mapped onto a map of a building. So my android app will regularly scan for nearby dongles and triangulate its location based on signal strength. The dongles location would be saved to a database along with their mac addresses to differentiate between them. The android phones location will then be sent to a server. This information will be used to show the phone’s location on a map of the building, or map of a route taken, on a website. My side project is to choose a suitable design pattern that could be implemented in this main project. I’m still a bit new to design patterns and am finding it hard to get my head around ones that may be suitable. I’ve heard maybe some that are aimed at web applications for the server side of things may be appropriate. My research so far is leading me to the following: Navigation Strategy Pattern Observer Pattern Command Pattern News Design Pattern Any advice would be a great help! Thanks

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  • Authorization design-pattern / practice?

    - by Lawtonfogle
    On one end, you have users. On the other end, you have activities. I was wondering if there is a best practice to relate the two. The simplest way I can think of is to have every activity have a role, and assign every user every role they need. The problem is that this gets really messy in practice as soon as you go beyond a trivial system. A way I recently designed was to have users who have roles, and roles have privileges, and activities require some combinations of privileges. For the trivial case, this is more complex, but I think it will scale better. But after I implemented it, I felt like it was overkill for the system I had. Another option would be to have users, who have roles, and activities require you to have a certain role to perform with many activities sharing roles. A more complex variant of this would given activities many possible roles, which you only needed one of. And an even more complex variant would be to allow logical statements of role ownership to use an activity (i.e. Must have A and (B exclusive or C) and must not have D). I could continue to list more, but I think this already gives a picture. And many of these have trade offs. But in software design, there are oftentimes solutions, while perhaps not perfect in every possible case, are clearly top of the pack to an extent it isn't even considered opinion based (i.e. how to store passwords, plain text is worse, hashing better, hashing and salt even better, despite the increased complexity of each level) (i.e. 2, Smart UI designs for applications are bad, even if it is subjective as to what the best design is). So, is there a best practice for authorization design that is not purely opinion based/subjective?

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  • Clean MVC design when there is viewer latency

    - by Tony Suffolk 66
    It isn't clear if this question has already been answered, so apologies in advance if this is a duplicate : I am implementing a game and trying to design around a clean MVC pattern - so my Control plane will implement the rules of the game (but not how the game is displayed), and the View plane implements how the game is displayed, and user iteraction - i.e. what game items or controls the user has activated. The challenge that I have is this : In my game the Control Plane can move game items more or less instaneously (The decision about what item to place where - and some of the initial consequences of that placement are reasonably trivial to calculate), but I want to design the Control Plane so that the View plane can display these movements either instaneously or using movement animations. The other complication is that player interaction must be locked out while those game items are moving (similar to chess - you can't attack an opposing piece as it moves past one of your pieces) So do I : Implement all the logic in the Control Plane asynchronously - and separate the descision making from the actions - so the Control plane decides piece 'A' needs to move to a given place - tells the view plane, and but does not implement the move in data until the view plane informs the control plane that the move/animation is complete. A lot of interlock points between the two layers. Implement all the control plane logic in one place - decisions and movement (keeping track of what moved where), and pass all the movements in one go to the View plane to do with what it will. Control Plane is almost fire and forget here. A hybrid of 1 & 2 - The control plane implements all the moves in a temporary data store - but maintains a second store which reflects what is actually visible to the viewer, based on calls and feedback from the View plane. All 3 are relatively easy to implement (target language is python), but having never done a clean MVC pattern with view latency before - I am not sure which design is best

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  • Design Book–Dimensional or No Dimensional, that is..the question

    - by drsql
    So, it is right there in the title of the book “Relational Database Design” etc (the title is kinda long :)  But as I consider what to cover and, conversely, what not to cover, dimensional design inevitably pops up. So I am considering including it in the book. One thing I try to do is to cover topics to a level where you can start using it immediately, and I am not sure that I could get a deep enough coverage of the subject to do that. I don’t really feel like it has to be the definitive source...(read more)

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  • Recommendations for books and training resources covering for Design for Programmers

    - by Jon Hopkins
    Off the back of one of the answers to this question (currently the second highest scoring), it made me think, what's the best way to get developers up to speed on good basic design principals. I'm not talking about making them into graphic designers but some developers almost take pride in ugly UIs, seeing them as unimportant next to the functionality. What primarily interested in are the graphic design elements rather than the usability aspects which is pretty well covered by books such as Don't Make Me Think. Use of white space, emphasis, font selection and a million other things I'm probably not even aware of. I know people are often seen as artistic or not artistic but surely the basics can be taught and someone has written a book covering this?

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  • Is this proper OO design for C++?

    - by user121917
    I recently took a software processes course and this is my first time attempting OO design on my own. I am trying to follow OO design principles and C++ conventions. I attempted and gave up on MVC for this application, but I am trying to "decouple" my classes such that they can be easily unit-tested and so that I can easily change the GUI library used and/or the target OS. At this time, I have finished designing classes but have not yet started implementing methods. The function of the software is to log all packets sent and received, and display them on the screen (like WireShark, but for one local process only). The software accomplishes this by hooking the send() and recv() functions in winsock32.dll, or some other pair of analogous functions depending on what the intended Target is. The hooks add packets to SendPacketList/RecvPacketList. The GuiLogic class starts a thread which checks for new packets. When new packets are found, it utilizes the PacketFilter class to determine the formatting for the new packet, and then sends it to MainWindow, a native win32 window (with intent to later port to Qt).1 Full size image of UML class diagram Here are my classes in skeleton/header form (this is my actual code): class PacketModel { protected: std::vector<byte> data; int id; public: PacketModel(); PacketModel(byte* data, unsigned int size); PacketModel(int id, byte* data, unsigned int size); int GetLen(); bool IsValid(); //len >= sizeof(opcode_t) opcode_t GetOpcode(); byte* GetData(); //returns &(data[0]) bool GetData(byte* outdata, int maxlen); void SetData(byte* pdata, int len); int GetId(); void SetId(int id); bool ParseData(char* instr); bool StringRepr(char* outstr); byte& operator[] (const int index); }; class SendPacket : public PacketModel { protected: byte* returnAddy; public: byte* GetReturnAddy(); void SetReturnAddy(byte* addy); }; class RecvPacket : public PacketModel { protected: byte* callAddy; public: byte* GetCallAddy(); void SetCallAddy(byte* addy); }; //problem: packets may be added to list at any time by any number of threads //solution: critical section associated with each packet list class Synch { public: void Enter(); void Leave(); }; template<class PacketType> class PacketList { private: static const int MAX_STORED_PACKETS = 1000; public: static const int DEFAULT_SHOWN_PACKETS = 100; private: vector<PacketType> list; Synch synch; //wrapper for critical section public: void AddPacket(PacketType* packet); PacketType* GetPacket(int id); int TotalPackets(); }; class SendPacketList : PacketList<SendPacket> { }; class RecvPacketList : PacketList<RecvPacket> { }; class Target //one socket { bool Send(SendPacket* packet); bool Inject(RecvPacket* packet); bool InitSendHook(SendPacketList* sendList); bool InitRecvHook(RecvPacketList* recvList); }; class FilterModel { private: opcode_t opcode; int colorID; bool bFilter; char name[41]; }; class FilterFile { private: FilterModel filter; public: void Save(); void Load(); FilterModel* GetFilter(opcode_t opcode); }; class PacketFilter { private: FilterFile filters; public: bool IsFiltered(opcode_t opcode); bool GetName(opcode_t opcode, char* namestr); //return false if name does not exist COLORREF GetColor(opcode_t opcode); //return default color if no custom color }; class GuiLogic { private: SendPacketList sendList; RecvPacketList recvList; PacketFilter packetFilter; void GetPacketRepr(PacketModel* packet); void ReadNew(); void AddToWindow(); public: void Refresh(); //called from thread void GetPacketInfo(int id); //called from MainWindow }; I'm looking for a general review of my OO design, use of UML, and use of C++ features. I especially just want to know if I'm doing anything considerably wrong. From what I've read, design review is on-topic for this site (and off-topic for the Code Review site). Any sort of feedback is greatly appreciated. Thanks for reading this.

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  • Design Pattern for Complex Data Modeling

    - by Aaron Hayman
    I'm developing a program that has a SQL database as a backing store. As a very broad description, the program itself allows a user to generate records in any number of user-defined tables and make connections between them. As for specs: Any record generated must be able to be connected to any other record in any other user table (excluding itself...the record, not the table). These "connections" are directional, and the list of connections a record has is user ordered. Moreover, a record must "know" of connections made from it to others as well as connections made to it from others. The connections are kind of the point of this program, so there is a strong possibility that the number of connections made is very high, especially if the user is using the software as intended. A record's field can also include aggregate information from it's connections (like obtaining average, sum, etc) that must be updated on change from another record it's connected to. To conserve memory, only relevant information must be loaded at any one time (can't load the entire database in memory at load and go from there). I cannot assume the backing store is local. Right now it is, but eventually this program will include syncing to a remote db. Neither the user tables, connections or records are known at design time as they are user generated. I've spent a lot of time trying to figure out how to design the backing store and the object model to best fit these specs. In my first design attempt on this, I had one object managing all a table's records and connections. I attempted this first because it kept the memory footprint smaller (records and connections were simple dicts), but maintaining aggregate and link information between tables became....onerous (ie...a huge spaghettified mess). Tracing dependencies using this method almost became impossible. Instead, I've settled on a distributed graph model where each record and connection is 'aware' of what's around it by managing it own data and connections to other records. Doing this increases my memory footprint but also let me create a faulting system so connections/records aren't loaded into memory until they're needed. It's also much easier to code: trace dependencies, eliminate cycling recursive updates, etc. My biggest problem is storing/loading the connections. I'm not happy with any of my current solutions/ideas so I wanted to ask and see if anybody else has any ideas of how this should be structured. Connections are fairly simple. They contain: fromRecordID, fromTableID, fromRecordOrder, toRecordID, toTableID, toRecordOrder. Here's what I've come up with so far: Store all the connections in one big table. If I do this, either I load all connections at once (one big db call) or make a call every time a user table is loaded. The big issue here: the size of the connections table has the potential to be huge, and I'm afraid it would slow things down. Store in separate tables all the outgoing connections for each user table. This is probably the worst idea I've had. Now my connections are 'spread out' over multiple tables (one for each user table), which means I have to make a separate DB called to each table (or make a huge join) just to find all the incoming connections for a particular user table. I've avoided making "one big ass table", but I'm not sure the cost is worth it. Store in separate tables all outgoing AND incoming connections for each user table (using a flag to distinguish between incoming vs outgoing). This is the idea I'm leaning towards, but it will essentially double the total DB storage for all the connections (as each connection will be stored in two tables). It also means I have to make sure connection information is kept in sync in both places. This is obviously not ideal but it does mean that when I load a user table, I only need to load one 'connection' table and have all the information I need. This also presents a separate problem, that of connection object creation. Since each user table has a list of all connections, there are two opportunities for a connection object to be made. However, connections objects (designed to facilitate communication between records) should only be created once. This means I'll have to devise a common caching/factory object to make sure only one connection object is made per connection. Does anybody have any ideas of a better way to do this? Once I've committed to a particular design pattern I'm pretty much stuck with it, so I want to make sure I've come up with the best one possible.

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  • Design Application to "Actively" Invite Users (pretend they have privileges)

    - by user3086451
    I am designing an application where users message one another privately, and may send messages to any Entity in the database (an Entity may not have a user account yet, it is a professional database). I am not sure how to best design the database and the API to allow messaging unregistered users. The application should remain secure, and data only accessed by those with correct permissions. Messages sent to persons without user accounts serve as an invitation. The invited person should be able to view the message, act on it, and complete the user registration upon receiving an InviteMessage. In simple terms, I have: User misc user fields (email, pw, dateJoined) Entity (large professional dataset): personalDetails... user->User (may be null) UserMessage: sender->User recipient->User dateCreated messageContent, other fields..... InviteMessage: sender->User recipient->Entity expiringUrl inviteeEmail inviteePhone I plan to alert the user when selecting a recipient that is not registered yet, and inform that he may send the message as an invitation by providing email, phone where we can send the invitation. Invitations will have a unique, one-time-use URL, e.g. uuid.uuid4(). When accessed, the invitee will see the InviteMessage and details about completing his/her registration profile. When registration is complete, InviteMessage details to a new instance of UserMessage (to not lose their data), and assign it to the newly created User. The ability to interact with and invite persons who do not yet have accounts is a key feature of the application, and it seems better to separate the invitation from the private, app messages (easier to keep functionality separate, better if data model changes). Is this a reasonable, good design? If not, what would you suggest? Do you have any improvements? Am I correct to choose to create a separate endpoint for creating invitations via the API?

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  • Recommened design pattern to handle multiple compression algorithms for a class hierarchy

    - by sgorozco
    For all you OOD experts. What would be the recommended way to model the following scenario? I have a certain class hierarchy similar to the following one: class Base { ... } class Derived1 : Base { ... } class Derived2 : Base { ... } ... Next, I would like to implement different compression/decompression engines for this hierarchy. (I already have code for several strategies that best handle different cases, like file compression, network stream compression, legacy system compression, etc.) I would like the compression strategy to be pluggable and chosen at runtime, however I'm not sure how to handle the class hierarchy. Currently I have a tighly-coupled design that looks like this: interface ICompressor { byte[] Compress(Base instance); } class Strategy1Compressor : ICompressor { byte[] Compress(Base instance) { // Common compression guts for Base class ... // if( instance is Derived1 ) { // Compression guts for Derived1 class } if( instance is Derived2 ) { // Compression guts for Derived2 class } // Additional compression logic to handle other class derivations ... } } As it is, whenever I add a new derived class inheriting from Base, I would have to modify all compression strategies to take into account this new class. Is there a design pattern that allows me to decouple this, and allow me to easily introduce more classes to the Base hierarchy and/or additional compression strategies?

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  • How do i mount my SD Card? I am using ubuntu 10.04

    - by shobhit
    root@shobhit:/media# lsusb Bus 002 Device 017: ID 14cd:125c Super Top Bus 002 Device 003: ID 0c45:6421 Microdia Bus 002 Device 002: ID 8087:0020 Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 001 Device 011: ID 413c:8160 Dell Computer Corp. Bus 001 Device 006: ID 413c:8162 Dell Computer Corp. Bus 001 Device 005: ID 413c:8161 Dell Computer Corp. Bus 001 Device 004: ID 138a:0008 DigitalPersona, Inc Bus 001 Device 003: ID 0a5c:4500 Broadcom Corp. BCM2046B1 USB 2.0 Hub (part of BCM2046 Bluetooth) Bus 001 Device 002: ID 8087:0020 Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub root@shobhit:/home/shobhit/scripts/internalUtilities# sudo lspci -v -nn 00:1a.0 USB Controller [0c03]: Intel Corporation 5 Series/3400 Series Chipset USB2 Enhanced Host Controller [8086:3b3c] (rev 06) (prog-if 20) Subsystem: Dell Device [1028:0441] Flags: bus master, medium devsel, latency 0, IRQ 16 Memory at fbc08000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] PCIe advanced features <?> Kernel driver in use: ehci_hcd 00:1d.0 USB Controller [0c03]: Intel Corporation 5 Series/3400 Series Chipset USB2 Enhanced Host Controller [8086:3b34] (rev 06) (prog-if 20) Subsystem: Dell Device [1028:0441] Flags: bus master, medium devsel, latency 0, IRQ 23 Memory at fbc07000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] PCIe advanced features <?> Kernel driver in use: ehci_hcd 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev a6) (prog-if 01) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=20, subordinate=20, sec-latency=32 Capabilities: [50] Subsystem: Dell Device [1028:0441] 00:1f.0 ISA bridge [0601]: Intel Corporation Mobile 5 Series Chipset LPC Interface Controller [8086:3b0b] (rev 06) Subsystem: Dell Device [1028:0441] Flags: bus master, medium devsel, latency 0 Capabilities: [e0] Vendor Specific Information <?> Kernel modules: iTCO_wdt 00:1f.2 SATA controller [0106]: Intel Corporation 5 Series/3400 Series Chipset 6 port SATA AHCI Controller [8086:3b2f] (rev 06) (prog-if 01) Subsystem: Dell Device [1028:0441] Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 29 I/O ports at f070 [size=8] I/O ports at f060 [size=4] I/O ports at f050 [size=8] I/O ports at f040 [size=4] I/O ports at f020 [size=32] Memory at fbc06000 (32-bit, non-prefetchable) [size=2K] Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Capabilities: [70] Power Management version 3 Capabilities: [a8] SATA HBA <?> Capabilities: [b0] PCIe advanced features <?> Kernel driver in use: ahci Kernel modules: ahci 00:1f.3 SMBus [0c05]: Intel Corporation 5 Series/3400 Series Chipset SMBus Controller [8086:3b30] (rev 06) Subsystem: Dell Device [1028:0441] Flags: medium devsel, IRQ 3 Memory at fbc05000 (64-bit, non-prefetchable) [size=256] I/O ports at f000 [size=32] Kernel modules: i2c-i801 00:1f.6 Signal processing controller [1180]: Intel Corporation 5 Series/3400 Series Chipset Thermal Subsystem [8086:3b32] (rev 06) Subsystem: Dell Device [1028:0441] Flags: bus master, fast devsel, latency 0, IRQ 3 Memory at fbc04000 (64-bit, non-prefetchable) [size=4K] Capabilities: [50] Power Management version 3 Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable- 12:00.0 Network controller [0280]: Broadcom Corporation Device [14e4:4727] (rev 01) Subsystem: Dell Device [1028:0010] Flags: bus master, fast devsel, latency 0, IRQ 17 Memory at fbb00000 (64-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Capabilities: [58] Vendor Specific Information <?> Capabilities: [48] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Capabilities: [d0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting <?> Capabilities: [13c] Virtual Channel <?> Capabilities: [160] Device Serial Number cb-c0-8b-ff-ff-38-00-00 Capabilities: [16c] Power Budgeting <?> Kernel driver in use: wl Kernel modules: wl 13:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 03) Subsystem: Dell Device [1028:0441] Flags: bus master, fast devsel, latency 0, IRQ 28 I/O ports at e000 [size=256] Memory at d0b04000 (64-bit, prefetchable) [size=4K] Memory at d0b00000 (64-bit, prefetchable) [size=16K] Expansion ROM at fba00000 [disabled] [size=128K] Capabilities: [40] Power Management version 3 Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable+ Capabilities: [70] Express Endpoint, MSI 01 Capabilities: [ac] MSI-X: Enable- Mask- TabSize=4 Capabilities: [cc] Vital Product Data <?> Capabilities: [100] Advanced Error Reporting <?> Capabilities: [140] Virtual Channel <?> Capabilities: [160] Device Serial Number 00-e0-4c-68-00-00-00-03 Kernel driver in use: r8169 Kernel modules: r8169 root@shobhit:/home/shobhit/scripts/internalUtilities# sudo lshw shobhit description: Portable Computer product: Vostro 3500 vendor: Dell Inc. version: A10 serial: FV1L3N1 width: 32 bits capabilities: smbios-2.6 dmi-2.6 smp-1.4 smp configuration: boot=normal chassis=portable cpus=2 uuid=44454C4C-5600-1031-804C-C6C04F334E31 *-core description: Motherboard product: 0G2R51 vendor: Dell Inc. physical id: 0 version: A10 serial: .FV1L3N1.CN7016612H00PW. slot: To Be Filled By O.E.M. *-cpu:0 description: CPU product: Intel(R) Core(TM) i5 CPU M 480 @ 2.67GHz vendor: Intel Corp. physical id: 4 bus info: cpu@0 version: 6.5.5 serial: 0002-0655-0000-0000-0000-0000 slot: CPU 1 size: 1197MHz capacity: 2926MHz width: 64 bits clock: 533MHz capabilities: boot fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx rdtscp x86-64 constant_tsc arch_perfmon pebs bts xtopology nonstop_tsc aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 popcnt lahf_lm ida arat tpr_shadow vnmi flexpriority ept vpid cpufreq configuration: id=4 *-cache:0 description: L1 cache physical id: 5 slot: L1-Cache size: 64KiB capacity: 64KiB capabilities: internal write-back unified *-cache:1 description: L2 cache physical id: 6 slot: L2-Cache size: 512KiB capacity: 512KiB capabilities: internal varies unified *-cache:2 description: L3 cache physical id: 7 slot: L3-Cache size: 3MiB capacity: 3MiB capabilities: internal varies unified *-logicalcpu:0 description: Logical CPU physical id: 4.1 width: 64 bits capabilities: logical *-logicalcpu:1 description: Logical CPU physical id: 4.2 width: 64 bits capabilities: logical *-logicalcpu:2 description: Logical CPU physical id: 4.3 width: 64 bits capabilities: logical *-logicalcpu:3 description: Logical CPU physical id: 4.4 width: 64 bits capabilities: logical *-logicalcpu:4 description: Logical CPU physical id: 4.5 width: 64 bits capabilities: logical *-logicalcpu:5 description: Logical CPU physical id: 4.6 width: 64 bits capabilities: logical *-logicalcpu:6 description: Logical CPU physical id: 4.7 width: 64 bits capabilities: logical *-logicalcpu:7 description: Logical CPU physical id: 4.8 width: 64 bits capabilities: logical *-logicalcpu:8 description: Logical CPU physical id: 4.9 width: 64 bits capabilities: logical *-logicalcpu:9 description: Logical CPU physical id: 4.a width: 64 bits capabilities: logical *-logicalcpu:10 description: Logical CPU physical id: 4.b width: 64 bits capabilities: logical *-logicalcpu:11 description: Logical CPU physical id: 4.c width: 64 bits capabilities: logical *-logicalcpu:12 description: Logical CPU physical id: 4.d width: 64 bits capabilities: logical *-logicalcpu:13 description: Logical CPU physical id: 4.e width: 64 bits capabilities: logical *-logicalcpu:14 description: Logical CPU physical id: 4.f width: 64 bits capabilities: logical *-logicalcpu:15 description: Logical CPU physical id: 4.10 width: 64 bits capabilities: logical *-memory description: System Memory physical id: 1d slot: System board or motherboard size: 3GiB *-bank:0 description: DIMM Synchronous 1333 MHz (0.8 ns) product: HMT112S6TFR8C-H9 vendor: AD80 physical id: 0 serial: 5525C935 slot: DIMM_A size: 1GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:1 description: DIMM Synchronous 1333 MHz (0.8 ns) product: HMT125S6TFR8C-H9 vendor: AD80 physical id: 1 serial: 3441D6CA slot: DIMM_B size: 2GiB width: 64 bits clock: 1333MHz (0.8ns) *-firmware description: BIOS vendor: Dell Inc. physical id: 0 version: A10 (10/25/2010) size: 64KiB capacity: 1984KiB capabilities: mca pci upgrade shadowing escd cdboot bootselect socketedrom edd int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb zipboot biosbootspecification *-cpu:1 physical id: 1 bus info: cpu@1 version: 6.5.5 serial: 0002-0655-0000-0000-0000-0000 size: 1197MHz capacity: 1197MHz capabilities: vmx ht cpufreq configuration: id=4 *-logicalcpu:0 description: Logical CPU physical id: 4.1 capabilities: logical *-logicalcpu:1 description: Logical CPU physical id: 4.2 capabilities: logical *-logicalcpu:2 description: Logical CPU physical id: 4.3 capabilities: logical *-logicalcpu:3 description: Logical CPU physical id: 4.4 capabilities: logical *-logicalcpu:4 description: Logical CPU physical id: 4.5 capabilities: logical *-logicalcpu:5 description: Logical CPU physical id: 4.6 capabilities: logical *-logicalcpu:6 description: Logical CPU physical id: 4.7 capabilities: logical *-logicalcpu:7 description: Logical CPU physical id: 4.8 capabilities: logical *-logicalcpu:8 description: Logical CPU physical id: 4.9 capabilities: logical *-logicalcpu:9 description: Logical CPU physical id: 4.a capabilities: logical *-logicalcpu:10 description: Logical CPU physical id: 4.b capabilities: logical *-logicalcpu:11 description: Logical CPU physical id: 4.c capabilities: logical *-logicalcpu:12 description: Logical CPU physical id: 4.d capabilities: logical *-logicalcpu:13 description: Logical CPU physical id: 4.e capabilities: logical *-logicalcpu:14 description: Logical CPU physical id: 4.f capabilities: logical *-logicalcpu:15 description: Logical CPU physical id: 4.10 capabilities: logical *-pci description: Host bridge product: Core Processor DRAM Controller vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 18 width: 32 bits clock: 33MHz configuration: driver=agpgart-intel resources: irq:0 *-display description: VGA compatible controller product: Core Processor Integrated Graphics Controller vendor: Intel Corporation physical id: 2 bus info: pci@0000:00:02.0 version: 18 width: 64 bits clock: 33MHz capabilities: msi pm bus_master cap_list rom configuration: driver=i915 latency=0 resources: irq:30 memory:fac00000-faffffff memory:c0000000-cfffffff(prefetchable) ioport:f080(size=8) *-communication UNCLAIMED description: Communication controller product: 5 Series/3400 Series Chipset HECI Controller vendor: Intel Corporation physical id: 16 bus info: pci@0000:00:16.0 version: 06 width: 64 bits clock: 33MHz capabilities: pm msi bus_master cap_list configuration: latency=0 resources: memory:fbc09000-fbc0900f *-usb:0 description: USB Controller product: 5 Series/3400 Series Chipset USB2 Enhanced Host Controller vendor: Intel Corporation physical id: 1a bus info: pci@0000:00:1a.0 version: 06 width: 32 bits clock: 33MHz capabilities: pm debug bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:16 memory:fbc08000-fbc083ff *-multimedia description: Audio device product: 5 Series/3400 Series Chipset High Definition Audio vendor: Intel Corporation physical id: 1b bus info: pci@0000:00:1b.0 version: 06 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=HDA Intel latency=0 resources: irq:22 memory:fbc00000-fbc03fff *-pci:0 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 1 vendor: Intel Corporation physical id: 1c bus info: pci@0000:00:1c.0 version: 06 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm bus_master cap_list configuration: driver=pcieport resources: irq:24 ioport:2000(size=4096) memory:bc000000-bc1fffff memory:bc200000-bc3fffff(prefetchable) *-pci:1 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 2 vendor: Intel Corporation physical id: 1c.1 bus info: pci@0000:00:1c.1 version: 06 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm bus_master cap_list configuration: driver=pcieport resources: irq:25 ioport:3000(size=4096) memory:fbb00000-fbbfffff memory:bc400000-bc5fffff(prefetchable) *-network description: Wireless interface product: Broadcom Corporation vendor: Broadcom Corporation physical id: 0 bus info: pci@0000:12:00.0 logical name: eth1 version: 01 serial: c0:cb:38:8b:aa:d8 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list ethernet physical wireless configuration: broadcast=yes driver=wl0 driverversion=5.60.48.36 ip=10.0.1.50 latency=0 multicast=yes wireless=IEEE 802.11 resources: irq:17 memory:fbb00000-fbb03fff *-pci:2 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 3 vendor: Intel Corporation physical id: 1c.2 bus info: pci@0000:00:1c.2 version: 06 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm bus_master cap_list configuration: driver=pcieport resources: irq:26 ioport:e000(size=4096) memory:fba00000-fbafffff ioport:d0b00000(size=1048576) *-network description: Ethernet interface product: RTL8111/8168B PCI Express Gigabit Ethernet controller vendor: Realtek Semiconductor Co., Ltd. physical id: 0 bus info: pci@0000:13:00.0 logical name: eth0 version: 03 serial: 78:2b:cb:cc:0e:2a size: 10MB/s capacity: 1GB/s width: 64 bits clock: 33MHz capabilities: pm msi pciexpress msix vpd bus_master cap_list rom ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=2.3LK-NAPI duplex=half latency=0 link=no multicast=yes port=MII speed=10MB/s resources: irq:28 ioport:e000(size=256) memory:d0b04000-d0b04fff(prefetchable) memory:d0b00000-d0b03fff(prefetchable) memory:fba00000-fba1ffff(prefetchable) *-pci:3 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 5 vendor: Intel Corporation physical id: 1c.4 bus info: pci@0000:00:1c.4 version: 06 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm bus_master cap_list configuration: driver=pcieport resources: irq:27 ioport:d000(size=4096) memory:fb000000-fb9fffff ioport:d0000000(size=10485760) *-usb:1 description: USB Controller product: 5 Series/3400 Series Chipset USB2 Enhanced Host Controller vendor: Intel Corporation physical id: 1d bus info: pci@0000:00:1d.0 version: 06 width: 32 bits clock: 33MHz capabilities: pm debug bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:23 memory:fbc07000-fbc073ff *-pci:4 description: PCI bridge product: 82801 Mobile PCI Bridge vendor: Intel Corporation physical id: 1e bus info: pci@0000:00:1e.0 version: a6 width: 32 bits clock: 33MHz capabilities: pci bus_master cap_list *-isa description: ISA bridge product: Mobile 5 Series Chipset LPC Interface Controller vendor: Intel Corporation physical id: 1f bus info: pci@0000:00:1f.0 version: 06 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-storage description: SATA controller product: 5 Series/3400 Series Chipset 6 port SATA AHCI Controller vendor: Intel Corporation physical id: 1f.2 bus info: pci@0000:00:1f.2 logical name: scsi0 logical name: scsi1 version: 06 width: 32 bits clock: 66MHz capabilities: storage msi pm bus_master cap_list emulated configuration: driver=ahci latency=0 resources: irq:29 ioport:f070(size=8) ioport:f060(size=4) ioport:f050(size=8) ioport:f040(size=4) ioport:f020(size=32) memory:fbc06000-fbc067ff *-disk description: ATA Disk product: WDC WD3200BEKT-7 vendor: Western Digital physical id: 0 bus info: scsi@0:0.0.0 logical name: /dev/sda version: 01.0 serial: WD-WX21AC0W1945 size: 298GiB (320GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=77e3ed41 *-volume:0 description: Windows NTFS volume physical id: 1 bus info: scsi@0:0.0.0,1 logical name: /dev/sda1 version: 3.1 serial: aa69-51c0 size: 98MiB capacity: 100MiB capabilities: primary bootable ntfs initialized configuration: clustersize=4096 created=2012-04-03 02:00:15 filesystem=ntfs label=System Reserved state=clean *-volume:1 description: Windows NTFS volume physical id: 2 bus info: scsi@0:0.0.0,2 logical name: /dev/sda2 version: 3.1 serial: 9854ff5c-1dea-a147-84a6-624e758f44b8 size: 48GiB capacity: 48GiB capabilities: primary ntfs initialized configuration: clustersize=4096 created=2012-04-10 13:55:31 filesystem=ntfs modified_by_chkdsk=true mounted_on_nt4=true resize_log_file=true state=dirty upgrade_on_mount=true *-volume:2 description: Extended partition physical id: 3 bus info: scsi@0:0.0.0,3 logical name: /dev/sda3 size: 48GiB capacity: 48GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume:0 description: Linux swap / Solaris partition physical id: 5 logical name: /dev/sda5 capacity: 1952MiB capabilities: nofs *-logicalvolume:1 description: Linux filesystem partition physical id: 6 logical name: /dev/sda6 logical name: / capacity: 46GiB configuration: mount.fstype=ext4 mount.options=rw,relatime,errors=remount-ro,barrier=1,data=ordered state=mounted *-volume:3 description: Windows NTFS volume physical id: 4 bus info: scsi@0:0.0.0,4 logical name: /dev/sda4 logical name: /media/56AA8094AA807273 version: 3.1 serial: 22a29e8d-56c7-9a4a-adea-528103948f6d size: 200GiB capacity: 200GiB capabilities: primary ntfs initialized configuration: clustersize=4096 created=2012-04-02 20:17:15 filesystem=ntfs modified_by_chkdsk=true mount.fstype=fuseblk mount.options=rw,nosuid,nodev,relatime,user_id=0,group_id=0,default_permissions,allow_other,blksize=4096 mounted_on_nt4=true resize_log_file=true state=mounted upgrade_on_mount=true *-cdrom description: DVD-RAM writer product: DVD+-RW TS-L633J vendor: TSSTcorp physical id: 1 bus info: scsi@1:0.0.0 logical name: /dev/cdrom logical name: /dev/cdrw logical name: /dev/dvd logical name: /dev/dvdrw logical name: /dev/scd0 logical name: /dev/sr0 version: D200 capabilities: removable audio cd-r cd-rw dvd dvd-r dvd-ram configuration: ansiversion=5 status=nodisc *-serial UNCLAIMED description: SMBus product: 5 Series/3400 Series Chipset SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci@0000:00:1f.3 version: 06 width: 64 bits clock: 33MHz configuration: latency=0 resources: memory:fbc05000-fbc050ff ioport:f000(size=32) *-generic UNCLAIMED description: Signal processing controller product: 5 Series/3400 Series Chipset Thermal Subsystem vendor: Intel Corporation physical id: 1f.6 bus info: pci@0000:00:1f.6 version: 06 width: 64 bits clock: 33MHz capabilities: pm msi bus_master cap_list configuration: latency=0 resources: memory:fbc04000-fbc04fff *-scsi physical id: 2 bus info: usb@2:1.1 logical name: scsi15 capabilities: emulated scsi-host configuration: driver=usb-storage *-disk description: SCSI Disk physical id: 0.0.0 bus info: scsi@15:0.0.0 logical name: /dev/sdb I have tried all options like fdisk /dev/sdb , pmount /dev/sdb but nothing is working .Pls guide me

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  • Should universities put more emphasis on teaching their students about design patterns?

    - by gablin
    While I've heard about design patterns being mentioned in a few courses at uni, I know of only a single course which actually teaches design patterns. In almost all other areas (algorithms, parallelism, architecture, dynamic languages, paradigms, etc), there are several, often a basic course and an advanced course. Should universities put more emphasis about teaching their students about design patterns and provide more courses in design patters? Are lack of knowledge about design patterns common in just-graduated junior developers?

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  • Which design pattern to use when using ORM?

    - by RPK
    I am writing a small ASP.NET Web Forms application. In my solution explorer, I added various class library projects to define layers, viz: Model Repository Presentation WebUI Someone suggested me that this layered approach is not of much sense if I am using ORM tool like PetaPoco, which itself takes care of separation of data access layer. I want to use PetaPoco micro-ORM and want to know which design pattern is suitable with ORM tools. Do I still need several class library projects to separate the concerns?

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  • Logical and Physical Modeling for Analytical Applications

    - by Dejan Sarka
    I am proud to announce that my first course for Pluralsight is released. The course title is Logical and Physical Modeling for Analytical Applications. Here is the description of the course. A bad data model leads to an application that does not perform well. Therefore, when developing an application, you should create a good data model from the start. However, even the best logical model can’t help when the physical implementation is bad. It is also important to know how SQL Server stores and accesses data, and how to optimize the data access. Database optimization starts by splitting transactional and analytical applications. In this course, you learn how to support analytical applications with logical design, get understanding of the problems with data access for queries that deal with large amounts of data, and learn about SQL Server optimizations that help solving these problems. Enjoy the course!

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  • Good Video Game User Interface Design Books/Websites?

    - by Tucker Morgan
    I having been programming games for some time, but while my teachers say that my code is good and advanced, my friends say that the interface is hard to understand and not the easiest to navigate. I want to learn how to design good user interfaces so that I can program better games, and people will have a easier time getting around. Does anyone know of any good books or websites about designing video game interfaces?

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  • Explanation needed, for “Ask, don't tell” approach?

    - by the_naive
    I'm taking a course on design patterns in software engineering and here I'm trying to understand the good and the bad way of design relating to "coupling" and "cohesion". I could not understand the concept described in the following image. The example of code shown in the image is ambiguous to me, so I can't quite clearly get what exactly "Ask, don't tell!" approach mean. Could you please explain?

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  • Design pattern for isomorphic trees

    - by Peregring-lk
    I want to create a data structure to work with isomorphic tree. I don't search for a "algorithms" or methods to check if two or more trees are isomorphic each other. Just to create various trees with the same structure. Example: 2 - - - - - - - 'a' - - - - - - - 3.5 / \ / \ / \ 3 3 'f' 'y' 1.0 3.1 / \ / \ / \ 4 7 'e' 'f' 2.3 7.7 The first "layer" or tree is the "natural tree" (a tree with natural numbers), the second layer is the "character tree" and the third one is the "float tree". The data structure has a method or iterator to traverse the tree and to make diferent operations with its values. These operations could change the value of nodes, but never its structure (first I create the structure and then I configure the tree with its diferent layers). In case of that I add a new node, this would be applied to each layer. Which known design pattern fits with this description or is related with it?

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  • Email Content creation | Proper design

    - by Umesh Awasthi
    Working on an E commerce application where we need to send so many email to customer like Registration email Forget Password Order placed There are many other emails that can be sent, I already have emailService in place which is responsible for sending email and It needs an Email object, Everything is working find, but I am struck at one point and not sure how best this can be done. We need to create content so as it can be passed to emailService and not sure how to design this. For example, in Customer registration, I have a customerFacade which is working between Controller and ServiceLayer, I just want to delegate this Email Content creation work away from Facade layer and to make it more flexible. Currently I am creating Registration email content inside customerFacade and some how I am not liking this way, since that means for each email, I need to create content in respective Facade. What is best way to go or current approach is fine enough?

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  • How to design application for scaling the application?

    - by Muhammad
    I have one application which handles hardware events connected on the same computer's PCIe slots. The maximum number of PCIe slots on motherboard are two. I have utilized both slots. Now for scaling the application I need either more PCIe slots in same computer or I use another computer. So consider I am using another computer with same application and hardware connected on the PCIe Slots. Now my problem is that I want to design application over it which can access both computers hardware devices and does the process on it. The processed data should be send back to the respective PC's hardware. Please refer the attached diagram for expansion.

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  • Design: How to model / where to store relational data between classes

    - by Walker
    I'm trying to figure out the best design here, and I can see multiple approaches, but none that seems "right." There are three relevant classes here: Base, TradingPost, and Resource. Each Base has a TradingPost which can offer various Resources depending on the Base's tech level. Where is the right place to store the minimum tech level a base must possess to offer any given resource? A database seems like overkill. Putting it in each subclass of Resource seems wrong--that's not an intrinsic property of the Resource. Do I have a mediating class, and if so, how does it work? It's important that I not be duplicating code; that I have one place where I set the required tech level for a given item. Essentially, where does this data belong? P.S. Feel free to change the title; I struggled to come up with one that fits.

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  • How to design console application with good seperation of UI from Logic

    - by JavaSa
    Is it considered an overkill for console application to be design like MVC , MVP or N tier architecture? If not which is more common and if you can link me to simple example of it. I want to implement a tic tac toe game in console application. I have a solution which hold two projects: TicTacToeBusinessLogic (Class library project) and TicTacToeConsoleApplication (Console application project) to represent the view logic. In the TicTacToeConsoleApplication I've Program.cs class which holds the main entry point (public static void Main). Now I face a problem. I want the game to handle its own game flow so I can: Create new GameManager class (from BL) but this causing the view to directly know the BL part. So I'm a little confused how to write it in an acceptable way. Should I use delegates? Please show me a simple example.

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  • Looking for some OO design advice

    - by Andrew Stephens
    I'm developing an app that will be used to open and close valves in an industrial environment, and was thinking of something simple like this:- public static void ValveController { public static void OpenValve(string valveName) { // Implementation to open the valve } public static void CloseValve(string valveName) { // Implementation to close the valve } } (The implementation would write a few bytes of data to the serial port to control the valve - an "address" derived from the valve name, and either a "1" or "0" to open or close the valve). Another dev asked whether we should instead create a separate class for each physical valve, of which there are dozens. I agree it would be nicer to write code like PlasmaValve.Open() rather than ValveController.OpenValve("plasma"), but is this overkill? Also, I was wondering how best to tackle the design with a couple of hypothetical future requirements in mind:- We are asked to support a new type of valve requiring different values to open and close it (not 0 and 1). We are asked to support a valve that can be set to any position from 0-100, rather than simply "open" or "closed". Normally I would use inheritance for this kind of thing, but I've recently started to get my head around "composition over inheritance" and wonder if there is a slicker solution to be had using composition?

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  • How to design a scriptable communication emulator?

    - by Hawk
    Requirement: We need a tool that simulates a hardware device that communicates via RS232 or TCP/IP to allow us to test our main application which will communicate with the device. Current flow: User loads script Parse script into commands User runs script Execute commands Script / commands (simplified for discussion): Connect RS232 = RS232ConnectCommand Connect TCP/IP = TcpIpConnectCommand Send data = SendCommand Receive data = ReceiveCommand Disconnect = DisconnectCommand All commands implement the ICommand interface. The command runner simply executes a sequence of ICommand implementations sequentially thus ICommand must have an Execute exposure, pseudo code: void Execute(ICommunicator context) The Execute method takes a context argument which allows the command implementations to execute what they need to do. For instance SendCommand will call context.Send, etc. The problem RS232ConnectCommand and TcpIpConnectCommand needs to instantiate the context to be used by subsequent commands. How do you handle this elegantly? Solution 1: Change ICommand Execute method to: ICommunicator Execute(ICommunicator context) While it will work it seems like a code smell. All commands now need to return the context which for all commands except the connection ones will be the same context that is passed in. Solution 2: Create an ICommunicatorWrapper (ICommunicationBroker?) which follows the decorator pattern and decorates ICommunicator. It introduces a new exposure: void SetCommunicator(ICommunicator communicator) And ICommand is changed to use the wrapper: void Execute(ICommunicationWrapper context) Seems like a cleaner solution. Question Is this a good design? Am I on the right track?

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  • C# vector class - Interpolation design decision

    - by Benjamin
    Currently I'm working on a vector class in C# and now I'm coming to the point, where I've to figure out, how i want to implement the functions for interpolation between two vectors. At first I came up with implementing the functions directly into the vector class... public class Vector3D { public static Vector3D LinearInterpolate(Vector3D vector1, Vector3D vector2, double factor) { ... } public Vector3D LinearInterpolate(Vector3D other, double factor { ... } } (I always offer both: a static method with two vectors as parameters and one non-static, with only one vector as parameter) ...but then I got the idea to use extension methods (defined in a seperate class called "Interpolation" for example), since interpolation isn't really a thing only available for vectors. So this could be another solution: public class Vector3D { ... } public static class Interpolation { public static Vector3D LinearInterpolate(this Vector3D vector, Vector3D other, double factor) { ... } } So here an example how you'd use the different possibilities: { var vec1 = new Vector3D(5, 3, 1); var vec2 = new Vector3D(4, 2, 0); Vector3D vec3; vec3 = vec1.LinearInterpolate(vec2, 0.5); //1 vec3 = Vector3D.LinearInterpolate(vec1, vec2, 0.5); //2 //or with extension-methods vec3 = vec1.LinearInterpolate(vec2, 0.5); //3 (same as 1) vec3 = Interpolation.LinearInterpolation(vec1, vec2, 0.5); //4 } So I really don't know which design is better. Also I don't know if there's an ultimate rule for things like this or if it's just about what someone personally prefers. But I really would like to hear your opinions, what's better (and if possible why ).

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  • Relative encapsulation design

    - by taher1992
    Let's say I am doing a 2D application with the following design: There is the Level object that manages the world, and there are world objects which are entities inside the Level object. A world object has a location and velocity, as well as size and a texture. However, a world object only exposes get properties. The set properties are private (or protected) and are only available to inherited classes. But of course, Level is responsible for these world objects, and must somehow be able to manipulate at least some of its private setters. But as of now, Level has no access, meaning world objects must change its private setters to public (violating encapsulation). How to tackle this problem? Should I just make everything public? Currently what I'm doing is having a inner class inside game object that does the set work. So when Level needs to update an objects location it goes something like this: void ChangeObject(GameObject targetObject, int newX, int newY){ // targetObject.SetX and targetObject.SetY cannot be set directly var setter = new GameObject.Setter(targetObject); setter.SetX(newX); setter.SetY(newY); } This code feels like overkill, but it doesn't feel right to have everything public so that anything can change an objects location for example.

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  • design for supporting entities with images

    - by brainydexter
    I have multiple entities like Hotels, Destination Cities etc which can contain images. The way I have my system setup right now is, I think of all the images belonging to this universal set (a table in the DB contains filePaths to all the images). When I have to add an image to an entity, I see if the entity exists in this universal set of images. If it exists, attach the reference to this image, else create a new image. E.g.: class ImageEntityHibernateDAO { public void addImageToEntity(IContainImage entity, String filePath, String title, String altText) { ImageEntity image = this.getImage(filePath); if (image == null) image = new ImageEntity(filePath, title, altText); getSession().beginTransaction(); entity.getImages().add(image); getSession().getTransaction().commit(); } } My question is: Earlier I had to write this code for each entity (and each entity would have a Set collection). So, instead of re-writing the same code, I created the following interface: public interface IContainImage { Set<ImageEntity> getImages(); } Entities which have image collections also implements IContainImage interface. Now, for any entity that needs to support adding Image functionality, all I have to invoke from the DAO looks something like this: // in DestinationDAO::addImageToDestination { imageDao.addImageToEntity(destination, imageFileName, imageTitle, imageAltText); // in HotelDAO::addImageToHotel { imageDao.addImageToEntity(hotel, imageFileName, imageTitle, imageAltText); It'd be great help if someone can provide me some critique on this design ? Are there any serious flaws that I'm not seeing right away ?

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