Search Results

Search found 571 results on 23 pages for 'registers'.

Page 2/23 | < Previous Page | 1 2 3 4 5 6 7 8 9 10 11 12  | Next Page >

  • Working with ieee format numbers in ARM

    - by Jake Sellers
    I'm trying to write an ARM program that will convert an ieee number to a TNS format number. TNS is a format used by some super computers, and is similar to ieee but different. I'm trying to use several masks to place the three different "part" of the ieee number in separate registers so I can move them around accordingly. Here is my unpack subroutine: UnpackIEEE LDR r1, SMASK ;load the sign bit mask into r1 LDR r2, EMASK ;load the exponent mask into r2 LDR r3, GMASK ;load the significand mask into r3 AND r4, r0, r1 ;apply sign mask to IEEE and save into r4 AND r5, r0, r2 ;apply exponent mask to IEEE and save into r5 AND r6, r0, r3 ;apply significand mask to IEEE and save into r6 MOV pc, r14 ;return And here are the masks and number declarations so you can understand: IEEE DCD 0x40300000 ;2.75 decimal or 01000000001100000000000000000000 binary SMASK DCD 0x80000000 ;Sign bit mask EMASK DCD 0x7F800000 ;Exponent mask GMASK DCD 0x007FFFFF ;Significand mask When I step through with the debugger, the results I get are not what I expect after working through it on paper. EDIT: What I mean, is that after the subroutine runs, registers 4, 5, and 6 all remain 0. I can't figure out why the masks are not working. I think I do not fully understand how the number is being stored in the register or using the masks wrong. Any help appreciated. If you need more info just ask. EDIT: entry point: Very simple, just trying to get these subroutines working. ENTRY LDR r1, IEEE ;load IEEE num into r1 BL UnpackIEEE ;call unpack sub SWI SWI_Exit ;finish

    Read the article

  • Could this code damage my processor??!!

    - by Osama Gamal
    A friend sent me that code and alleges that it could damage the processor. Is that true? void damage_processor() { while (true) { // Assembly code that sets the five control registers bits to ones which causes a bunch of exceptions in the system and then damages the processor Asm( "mov cr0, 0xffffffff \n\t" "mov cr1, 0xffffffff \n\t" "mov cr2, 0xffffffff \n\t" "mov cr3, 0xffffffff \n\t" "mov cr4, 0xffffffff \n\t" ) } } Is that true?

    Read the article

  • NEC uPD720200 USB 3.0 not working on Ubuntu 12.04

    - by Jagged
    I've recently installed Ubuntu 12.04 64-bit on a HP Envy 15 1104tx. Most stuff appears to be working fine with the exception of the two USB3 ports (USB2 port works fine). I've read a lot of articles but so far have not been able to find a solution. I've tried adding 'pci=nomsi' to '/etc/default/grub' but this made no difference. Some articles suggest booting into Windows and upgrading the firmware on the uPD720200. Any body had any experience of this? Is there a way I can checked the firmware version of the NEC uPD720200 in Linux to see if there is an update available? Any help appreciated. uname -a: Linux HP-ENVY-15-1104tx 3.2.0-26-generic #41-Ubuntu SMP Thu Jun 14 17:49:24 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux lshw: hp-envy-15-1104tx description: Notebook product: HP ENVY 15 Notebook PC (WF591PA#ABG) vendor: Hewlett-Packard version: 0492110000241910001420000 serial: CNF0301C79 width: 64 bits capabilities: smbios-2.6 dmi-2.6 vsyscall32 configuration: boot=normal chassis=notebook family=103C_5335KV sku=WF591PA#ABG uuid=434E4630-3330-3143-3739-60EB6906688F *-core description: Motherboard product: 1522 vendor: Hewlett-Packard physical id: 0 version: 36.35 serial: CNF0301C79 slot: Base Board Chassis Location *-firmware description: BIOS vendor: Hewlett-Packard physical id: 0 version: F.2B date: 10/12/2010 size: 1MiB capacity: 1472KiB capabilities: pci upgrade shadowing cdboot bootselect edd int13floppynec int13floppytoshiba int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int9keyboard int10video acpi usb biosbootspecification *-memory description: System Memory physical id: 13 slot: System board or motherboard size: 16GiB *-bank:0 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 0 serial: E13C4316 slot: Bottom size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:1 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 1 serial: E03C3E16 slot: Bottom size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:2 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 2 serial: 672279CC slot: On Board size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:3 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 3 serial: 652286CC slot: On Board size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-cpu description: CPU product: Intel(R) Core(TM) i7 CPU Q 820 @ 1.73GHz vendor: Intel Corp. physical id: 1d bus info: cpu@0 version: Intel(R) Core(TM) i7 CPU Q 820 @ 1.73GHz slot: CPU size: 1199MHz capacity: 1199MHz width: 64 bits clock: 1066MHz capabilities: x86-64 fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 popcnt lahf_lm ida tpr_shadow vnmi flexpriority ept vpid cpufreq configuration: cores=4 enabledcores=4 threads=8 *-cache:0 description: L3 cache physical id: 1e slot: L3 Cache size: 8MiB capacity: 8MiB capabilities: synchronous internal write-through unified *-cache:1 description: L2 cache physical id: 20 slot: L2 Cache size: 256KiB capacity: 256KiB capabilities: synchronous internal write-through unified *-cache:2 description: L1 cache physical id: 21 slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through instruction *-cache description: L1 cache physical id: 1f slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through data *-pci:0 description: Host bridge product: Core Processor DMI vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 11 width: 32 bits clock: 33MHz *-pci:0 description: PCI bridge product: Core Processor PCI Express Root Port 1 vendor: Intel Corporation physical id: 3 bus info: pci@0000:00:03.0 version: 11 width: 32 bits clock: 33MHz capabilities: pci msi pciexpress pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 ioport:4000(size=4096) memory:d4100000-d41fffff ioport:c0000000(size=268435456) *-display description: VGA compatible controller product: Broadway PRO [Mobility Radeon HD 5800 Series] vendor: Hynix Semiconductor (Hyundai Electronics) physical id: 0 bus info: pci@0000:01:00.0 version: 00 width: 64 bits clock: 33MHz capabilities: pm pciexpress msi vga_controller bus_master cap_list rom configuration: driver=fglrx_pci latency=0 resources: irq:58 memory:c0000000-cfffffff memory:d4100000-d411ffff ioport:4000(size=256) memory:d4140000-d415ffff *-multimedia description: Audio device product: Juniper HDMI Audio [Radeon HD 5700 Series] vendor: Hynix Semiconductor (Hyundai Electronics) physical id: 0.1 bus info: pci@0000:01:00.1 version: 00 width: 64 bits clock: 33MHz capabilities: pm pciexpress msi bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:56 memory:d4120000-d4123fff *-pci:1 description: PCI bridge product: Core Processor PCI Express Root Port 3 vendor: Intel Corporation physical id: 5 bus info: pci@0000:00:05.0 version: 11 width: 32 bits clock: 33MHz capabilities: pci msi pciexpress pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 memory:d4000000-d40fffff *-usb description: USB controller product: uPD720200 USB 3.0 Host Controller vendor: NEC Corporation physical id: 0 bus info: pci@0000:02:00.0 version: 03 width: 64 bits clock: 33MHz capabilities: pm msi msix pciexpress xhci bus_master cap_list configuration: driver=xhci_hcd latency=0 resources: irq:16 memory:d4000000-d4001fff *-generic:0 UNCLAIMED description: System peripheral product: Core Processor System Management Registers vendor: Intel Corporation physical id: 8 bus info: pci@0000:00:08.0 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:1 UNCLAIMED description: System peripheral product: Core Processor Semaphore and Scratchpad Registers vendor: Intel Corporation physical id: 8.1 bus info: pci@0000:00:08.1 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:2 UNCLAIMED description: System peripheral product: Core Processor System Control and Status Registers vendor: Intel Corporation physical id: 8.2 bus info: pci@0000:00:08.2 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:3 UNCLAIMED description: System peripheral product: Core Processor Miscellaneous Registers vendor: Intel Corporation physical id: 8.3 bus info: pci@0000:00:08.3 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-generic:4 UNCLAIMED description: System peripheral product: Core Processor QPI Link vendor: Intel Corporation physical id: 10 bus info: pci@0000:00:10.0 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-generic:5 UNCLAIMED description: System peripheral product: Core Processor QPI Routing and Protocol Registers vendor: Intel Corporation physical id: 10.1 bus info: pci@0000:00:10.1 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-multimedia description: Audio device product: 5 Series/3400 Series Chipset High Definition Audio vendor: Intel Corporation physical id: 1b bus info: pci@0000:00:1b.0 version: 05 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:55 memory:d4200000-d4203fff *-pci:2 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 1 vendor: Intel Corporation physical id: 1c bus info: pci@0000:00:1c.0 version: 05 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:17 ioport:3000(size=4096) memory:d3000000-d3ffffff ioport:d0000000(size=16777216) *-network description: Wireless interface product: Centrino Advanced-N 6200 vendor: Intel Corporation physical id: 0 bus info: pci@0000:03:00.0 logical name: wlan0 version: 35 serial: 00:27:10:40:e4:68 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list ethernet physical wireless configuration: broadcast=yes driver=iwlwifi driverversion=3.2.0-26-generic firmware=9.221.4.1 build 25532 latency=0 link=no multicast=yes wireless=IEEE 802.11abgn resources: irq:54 memory:d3000000-d3001fff *-pci:3 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 2 vendor: Intel Corporation physical id: 1c.1 bus info: pci@0000:00:1c.1 version: 05 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 ioport:2000(size=4096) memory:d2000000-d2ffffff ioport:d1000000(size=16777216) *-network description: Ethernet interface product: AR8131 Gigabit Ethernet vendor: Atheros Communications Inc. physical id: 0 bus info: pci@0000:04:00.0 logical name: eth0 version: c0 serial: 60:eb:69:06:68:8f size: 1Gbit/s capacity: 1Gbit/s width: 64 bits clock: 33MHz capabilities: pm msi pciexpress vpd bus_master cap_list ethernet physical tp 10bt 10bt-fd 100bt 100bt-fd 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=atl1c driverversion=1.0.1.0-NAPI duplex=full firmware=N/A ip=10.161.0.147 latency=0 link=yes multicast=yes port=twisted pair speed=1Gbit/s resources: irq:57 memory:d2000000-d203ffff ioport:2000(size=128) *-usb description: USB controller product: 5 Series/3400 Series Chipset USB2 Enhanced Host Controller vendor: Intel Corporation physical id: 1d bus info: pci@0000:00:1d.0 version: 05 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:20 memory:d4205800-d4205bff *-pci:4 description: PCI bridge product: 82801 Mobile PCI Bridge vendor: Intel Corporation physical id: 1e bus info: pci@0000:00:1e.0 version: a5 width: 32 bits clock: 33MHz capabilities: pci subtractive_decode bus_master cap_list *-isa description: ISA bridge product: Mobile 5 Series Chipset LPC Interface Controller vendor: Intel Corporation physical id: 1f bus info: pci@0000:00:1f.0 version: 05 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-storage description: RAID bus controller product: 82801 Mobile SATA Controller [RAID mode] vendor: Intel Corporation physical id: 1f.2 bus info: pci@0000:00:1f.2 logical name: scsi0 version: 05 width: 32 bits clock: 66MHz capabilities: storage msi pm bus_master cap_list emulated configuration: driver=ahci latency=0 resources: irq:45 ioport:5048(size=8) ioport:5054(size=4) ioport:5040(size=8) ioport:5050(size=4) ioport:5020(size=32) memory:d4205000-d42057ff *-disk description: ATA Disk product: OCZ-VERTEX3 physical id: 0.0.0 bus info: scsi@0:0.0.0 logical name: /dev/sda version: 2.15 serial: OCZ-0350P6H316X5KUQE size: 223GiB (240GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=000592dd *-volume:0 description: EXT4 volume vendor: Linux physical id: 1 bus info: scsi@0:0.0.0,1 logical name: /dev/sda1 logical name: / version: 1.0 serial: e741f18c-cfc5-4bce-b1e7-f80e517a3a22 size: 207GiB capacity: 207GiB capabilities: primary bootable journaled extended_attributes large_files huge_files dir_nlink recover extents ext4 ext2 initialized configuration: created=2012-06-15 06:49:27 filesystem=ext4 lastmountpoint=/ modified=2012-06-14 21:23:42 mount.fstype=ext4 mount.options=rw,relatime,errors=remount-ro,user_xattr,barrier=1,data=ordered mounted=2012-07-10 16:18:20 state=mounted *-volume:1 description: Extended partition physical id: 2 bus info: scsi@0:0.0.0,2 logical name: /dev/sda2 size: 15GiB capacity: 15GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume description: Linux swap / Solaris partition physical id: 5 logical name: /dev/sda5 capacity: 15GiB capabilities: nofs *-serial UNCLAIMED description: SMBus product: 5 Series/3400 Series Chipset SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci@0000:00:1f.3 version: 05 width: 64 bits clock: 33MHz configuration: latency=0 resources: memory:d4205c00-d4205cff ioport:5000(size=32) *-pci:1 description: Host bridge product: Core Processor QuickPath Architecture Generic Non-Core Registers vendor: Intel Corporation physical id: 101 bus info: pci@0000:ff:00.0 version: 04 width: 32 bits clock: 33MHz *-pci:2 description: Host bridge product: Core Processor QuickPath Architecture System Address Decoder vendor: Intel Corporation physical id: 102 bus info: pci@0000:ff:00.1 version: 04 width: 32 bits clock: 33MHz *-pci:3 description: Host bridge product: Core Processor QPI Link 0 vendor: Intel Corporation physical id: 103 bus info: pci@0000:ff:02.0 version: 04 width: 32 bits clock: 33MHz *-pci:4 description: Host bridge product: Core Processor QPI Physical 0 vendor: Intel Corporation physical id: 104 bus info: pci@0000:ff:02.1 version: 04 width: 32 bits clock: 33MHz *-pci:5 description: Host bridge product: Core Processor Integrated Memory Controller vendor: Intel Corporation physical id: 105 bus info: pci@0000:ff:03.0 version: 04 width: 32 bits clock: 33MHz *-pci:6 description: Host bridge product: Core Processor Integrated Memory Controller Target Address Decoder vendor: Intel Corporation physical id: 106 bus info: pci@0000:ff:03.1 version: 04 width: 32 bits clock: 33MHz *-pci:7 description: Host bridge product: Core Processor Integrated Memory Controller Test Registers vendor: Intel Corporation physical id: 107 bus info: pci@0000:ff:03.4 version: 04 width: 32 bits clock: 33MHz *-pci:8 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Control Registers vendor: Intel Corporation physical id: 108 bus info: pci@0000:ff:04.0 version: 04 width: 32 bits clock: 33MHz *-pci:9 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Address Registers vendor: Intel Corporation physical id: 109 bus info: pci@0000:ff:04.1 version: 04 width: 32 bits clock: 33MHz *-pci:10 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Rank Registers vendor: Intel Corporation physical id: 10a bus info: pci@0000:ff:04.2 version: 04 width: 32 bits clock: 33MHz *-pci:11 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Thermal Control Registers vendor: Intel Corporation physical id: 10b bus info: pci@0000:ff:04.3 version: 04 width: 32 bits clock: 33MHz *-pci:12 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Control Registers vendor: Intel Corporation physical id: 10c bus info: pci@0000:ff:05.0 version: 04 width: 32 bits clock: 33MHz *-pci:13 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Address Registers vendor: Intel Corporation physical id: 10d bus info: pci@0000:ff:05.1 version: 04 width: 32 bits clock: 33MHz *-pci:14 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Rank Registers vendor: Intel Corporation physical id: 10e bus info: pci@0000:ff:05.2 version: 04 width: 32 bits clock: 33MHz *-pci:15 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Thermal Control Registers vendor: Intel Corporation physical id: 10f bus info: pci@0000:ff:05.3 version: 04 width: 32 bits clock: 33MHz *-battery description: Lithium Ion Battery product: NK06053 vendor: SMP-ATL24 physical id: 1 slot: Primary capacity: 4800mWh configuration: voltage=11.1V lspci: 02:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 03) (prog-if 30 [XHCI]) Subsystem: Hewlett-Packard Company Device 1522 Flags: bus master, fast devsel, latency 0, IRQ 16 Memory at d4000000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Capabilities: [90] MSI-X: Enable+ Count=8 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number ff-ff-ff-ff-ff-ff-ff-ff Capabilities: [150] Latency Tolerance Reporting Kernel driver in use: xhci_hcd lsusb (with thumb drive plugged into USB3 port): Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 003 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 001 Device 002: ID 8087:0020 Intel Corp. Integrated Rate Matching Hub Bus 001 Device 003: ID 5986:01d0 Acer, Inc Bus 001 Device 004: ID 03f0:231d Hewlett-Packard

    Read the article

  • CPUID on Intel i7 processors

    - by StarPacker
    I'm having an issue with my CPUID-based code on newer i7-based machines. It is detecting the CPU as having a single core with 8 HT units instead of 4 cores each with 2 HT units. I must be misinterpreting the results of the CPUID information coming back from the CPU, but I can't see how. Basically, I iterate through each processor visible to Windows, set thread affinity to that thread and then make a sequence of CPUID calls. args = new CPUID_Args(); args.eax = 1; executeHandler(ref args); if (0 != (args.edx & (0x1 << 28))) { //If the 28th bit in EDX is flagged, this processor supports multiple logical processors per physical package // in this case bits 23:16 of EBX should give the count. //** EBX here is 0x2100800 logicalProcessorCount = (args.ebx & 0x00FF0000) >> 16; //** this tells me there are 16 logical processors (wrong) } else { logicalProcessorCount = 1; } apic = unchecked((byte)((0xFF000000 & args.ebx) >> 24)); if (maximumSupportedCPUID >= 4) { args = new CPUID_Args(); args.eax = 4; executeHandler(ref args); //EAX now contains 0x1C004121 coreCount = 1 + ((args.eax & 0xFC000000) >> 26); //This calculates coreCount as 8 } else { coreCount = 1; } This sequence repeats for the remainder of the CPUs in the system. Has anyone faced this before?

    Read the article

  • Quick, beginner MASM register question - DX:AX

    - by Francisco P.
    Hello, I am currently studying for an exam I'll have on x86 assembly. I didn't have much luck googling for ":", too common of a punctuation mark :/ IDIV - Signed Integer Division Usage: IDIV src Modifies flags: (AF,CF,OF,PF,SF,ZF undefined) Signed binary division of accumulator by source. If source is a byte value, AX is divided by "src" and the quotient is stored in AL and the remainder in AH. If source is a word value, DX:AX is divided by "src", and the quotient is stored in AL and the remainder in DX. Taken from "Intel Opcodes and Mnemonics" What does DX:AX mean? Thanks a lot for your time :)

    Read the article

  • Vim Register Use in Ex Mode

    - by Peck
    Potentially 2 questions in one. I would like to know how to reference a register in Ex mode. For instance, I'm editing a file and I want to save the file with a timestamp (or just datestamp really) appended to it. I know I can set register to the value of a shell commands output using: :let @a = system("date +\"%Y-%m-%d\"") Is there any to dereference this register and insert its value into an Ex command? Something like: :w testfile.<value of "a register> Copying to the system clipboard and pasting would be nice, but doing it in a more generic/programitic way for building on other commands in the future would be nice.

    Read the article

  • Most Efficient way to set Register to 1 or (-1)

    - by Bob
    I am taking an assembly course now, and the guy who checks our home assignments is a very pedantic old-school optimization freak. For example he deducts 10% if he sees: mov ax, 0 instead of: xor ax,ax even if it's only used once. I am not a complete beginner in assembly programing but I'm not an optimization expert, so I need your help in something (might be a very stupid question but I'll ask anyway): if I need to set a register value to 1 or (-1) is it better to use: mov ax, 1 or do something like: xor ax,ax inc ax I really need a good grade, so I'm trying to get it as optimized as possible. ( I need to optimize both time and code size)

    Read the article

  • Simple way to print value of a register in x86 assembly.

    - by Bob
    I need to write a program in 8086 Assembly that receives data from the user, does some mathematical calculations and prints the answer on the screen, I have written all parts of the program and all work fine but I don't know how to print the number to the screen. At the end of all my calculation the answer is AX and it is treated as an unsigned 16 bit integer. How do I print the decimal (unsigned) value of the AX register?

    Read the article

  • How is the implicit segment register of a near pointer determined?

    - by Daniel Trebbien
    In section 4.3 of Intel 64® and IA-32 Architectures Software Developer's Manual. Volume 1: Basic Architecture, it says: A near pointer is a 32-bit offset ... within a segment. Near pointers are used for all memory references in a flat memory model or for references in a segmented model where the identity of the segment being accessed is implied. This leads me to wondering: how is the implied segment register determined? I know that (%eip) and displaced (%eip) (e.g. -4(%eip)) addresses use %cs by default, and that (%esp) and displaced (%esp) addresses use %ss, but what about (%eax), (%edx), (%edi), (%ebp) etc., and can the implicit segment register depend also on the instruction that the memory address operand appears in?

    Read the article

  • Grep without storing search to the "/ register in Vim

    - by Phro
    In my .vimrc I have a mapping that makes a line of text 'title capitalized': noremap <Leader>at :s/\v<(.)(\w{2,})/\u\1\L\2/g<CR> However, whenever I run this function, it highlights every word that is at least three characters long in my entire document. Of course I could get this behaviour to stop simply by appending :nohlsearch<CR> to the end of the mapping, but this is more of an awkward hack that still avoids a bigger problem: The last search has been replaced by \v<(.)(\w{2,}). Is there any way to use the search commands in Vim without storing the last search in the "/ register; a 'silent' search of sorts? That way, after running this title-making command, I can still use my previous search to navigate the document using n, N, etc. Edit Using @brettanomyces' answer, I found that simply setting the mapping: noremap <Leader>at :call setline(line('.'),substitute(getline('.'), '\v<(.)(\w{2,})', '\u\1\L\2', 'g'))<CR> will successfully perform the substitution without storing the searched text into the / register.

    Read the article

  • Accessing the MSP and PSP registers of the Cortex-M3 in C/C++ code using Keil's µVision

    - by Captain NedD
    I need to access the MSP and PSP registers (the main and process stack registers) of the Cortex-M3 processor. I'm writing in C/C++. The µVision and associated compiler doesn't let you do inline assembly for this Thumb-2 only core (and I'm not sure that'd be such a good idea anyway). I need to do this so that I can extract the immediate value of an svc instruction regardless of whether it was executed while in thread or handler mode. Thanks,

    Read the article

  • Wireless device bug on 13.10. BCM4313 registers as eth1 instead of wlan0 and no internet access

    - by user205691
    My Hotel wiFi requires me to login with a username & password after connecting to the hotspot. So, my browser would open a page with username & passwrd fields to login and then connect to internet. But unfortunately, firefox & chromium dont seem to work. i dont think it is browser related but a setting for the wifi router or driver which is creating this issue. using Broadcom 801.11 STA wireless driver (proprietary). tried open source as well but same result !! The image linked below shows my wifi connection setting & Chromium. The login page itself comes up after a long time and after entering the credentials, it keeps loading for ever !! it is the same case for every other browser.. so i dont think its browser issue but something to do with wifi setting or network manager stuff.. interestingly, i am able to connect to WiFi networks with WPA key without any issue. Adhoc hotspot is a problem and that is my regular home network :( .. I hope i can get some help solving this issue ! I have tried repeating the same hotspot after login from my android, by creating a virtual repeater with WPA key and it works. I can browse on ubuntu using this method.. but cant be doing this regularly ! I tried loading the same login page of the hotel wifi while browsing through my repeater wifi created on mobile and screen shot attached below. the page loads up quick and easy.. so this means something is wrong with the way network manager handles adhoc connectivity & login ?? i installed wicd0 but it crashes on startup and not helpful at all ! Screenshot of Chromium page Login page with repeated hotspot ifconfig in my terminal results: krishna@krishna-HP-ENVY-4-Notebook-PC:~$ ifconfig eth0 Link encap:Ethernet HWaddr 28:92:4a:1d:54:fa UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) eth1 Link encap:Ethernet HWaddr e0:06:e6:89:fa:49 inet addr:10.24.1.71 Bcast:10.24.1.255 Mask:255.255.255.0 inet6 addr: fe80::e206:e6ff:fe89:fa49/64 Scope:Link UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:10940 errors:0 dropped:0 overruns:0 frame:348431 TX packets:6611 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:7669631 (7.6 MB) TX bytes:864195 (864.1 KB) Interrupt:17 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:2146 errors:0 dropped:0 overruns:0 frame:0 TX packets:2146 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:0 RX bytes:166120 (166.1 KB) TX bytes:166120 (166.1 KB) I wonder why is the wireless configured under eth1 ? I think this is a bug with earlier ubuntu versions, but is this normal in 13.10 or is there a wrong configuration here ? The wireless device in my pc is BCM4313 and i have installed the bcmwl-kernel-sources, wireless-tools to support the device. i also reinstalled the bcmwl-kernel as suggested on broadcom website, via synaptic package manager. Nothing has changed this situation ! I tried booting into liveUSB and then ifconfig results show wireless under wlan0. But then the wireless connects and loads the login page. So is the problem with the device configuration now ? i really want to get this fixed before i start configuring the other stuff like ATI graphics and such on the laptop for overheating.. lack of internet access is too bad a bug for me :P any help is appreciated!

    Read the article

  • Why is Read-Modify-Write necessary for registers on embedded systems?

    - by Adam Shiemke
    I was reading http://embeddedgurus.com/embedded-bridge/2010/03/different-bit-types-in-different-registers/, which said: With read/write bits, firmware sets and clears bits when needed. It typically first reads the register, modifies the desired bit, then writes the modified value back out and I have run into that consrtuct while maintaining some production code coded by old salt embedded guys here. I don't understand why this is necessary. When I want to set/clear a bit, I always just or/nand with a bitmask. To my mind, this solves any threadsafe problems, since I assume setting (either by assignment or oring with a mask) a register only takes one cycle. On the other hand, if you first read the register, then modify, then write, an interrupt happening between the read and write may result in writing an old value to the register. So why read-modify-write? Is it still necessary?

    Read the article

  • How do I write x86 Debug registers from user space on OSX?

    - by nall
    I'd like to play around with the debug MSRs defined in the x86 spec (DR0-7) from my OSX user-space program. Unfortunately, these require CPL == 0 (aka ring 0). I've thumbed through the OSX syscalls and with the exception of kernel_debug nothing really jumps out as a way to access these. It may be the case that they are only available via some higher level interface like kernel_debug, but it's unclear to me if that's the case or if I just haven't found the magic invocation to get to them. Anyone know how to do this?

    Read the article

  • Is there any way to get MSVC to pass structs arguments in registers on x64?

    - by Luke
    For a function with signature: struct Pair { void *v1, *v2 }; void f(Pair p); compiled on x64, I would like Pair's fields to be passed via register, as if the function was: void f(void *v1, void *v2); Compiling a test with gcc 4.2.1 for x86_64 on OSX 10.6, I can see this is exactly what happens by examining the disassembly. However, compiling with MSVC 2008 for x64 on Windows, the disassembly shows that Pair is passed on the stack. I understand that platform ABIs can prevent this optimization; does anyone know any MSVC-specific annotations, calling conventions, flags, or other hacks that can get this to work? Thank you!

    Read the article

  • x86 Assembly: Before Making a System Call on Linux Should You Save All Registers?

    - by mudge
    I have the below code that opens up a file, reads it into a buffer and then closes the file. The close file system call requires that the file descriptor number be in the ebx register. The ebx register gets the file descriptor number before the read system call is made. My question is should I save the ebx register on the stack or somewhere before I make the read system call, (could int 80h trash the ebx register?). And then restore the ebx register for the close system call? Or is the code I have below fine and safe? I have run the below code and it works, I'm just not sure if it is generally considered good assembly practice or not because I don't save the ebx register before the int 80h read call. ;; open up the input file mov eax,5 ; open file system call number mov ebx,[esp+8] ; null terminated string file name, first command line parameter mov ecx,0o ; access type: O_RDONLY int 80h ; file handle or negative error number put in eax test eax,eax js Error ; test sign flag (SF) for negative number which signals error ;; read in the full input file mov ebx,eax ; assign input file descripter mov eax,3 ; read system call number mov ecx,InputBuff ; buffer to read into mov edx,INPUT_BUFF_LEN ; total bytes to read int 80h test eax,eax js Error ; if eax is negative then error jz Error ; if no bytes were read then error add eax,InputBuff ; add size of input to the begining of InputBuff location mov [InputEnd],eax ; assign address of end of input ;; close the input file ;; file descripter is already in ebx mov eax,6 ; close file system call number int 80h

    Read the article

  • Organization &amp; Architecture UNISA Studies &ndash; Chap 13

    - by MarkPearl
    Learning Outcomes Explain the advantages of using a large number of registers Discuss the way in which compilers optimize register usage Discuss the evolution of CISC machines Describe the characteristics of RISC architecture Discuss the RISC vs. CISC controversy Describe the way in which RISC and CISC design principles can be combined Instruction Execution Characteristics To understand the the line of reasoning of RISC advocates, we need a brief overview of instruction execution characteristics. These include… Operations Operands Procedure Calls These three sections can be studied in depth in the textbook at pages 503 - 505 A number of groups have come up with the conclusion that the attempt to make the instruction set architecture closer to HLLs (High Level Languages) is not the most effective design strategy. Rather HLL’s can be best supported by optimizing performance of the most time-consuming features of typical HLL programs. Generally 3 main characteristics came up to improve performance… Use a large number of registers or use a compiler to optimize register usage Careful attention needs to be paid to the design of instruction pipelines A simplified (reduced) instruction set is indicated The use of a large register optimization One of the most important design principles of RISC machines is the use of a large number of registers. The concept of register windows and the use of a large register file versus the use of cache memory are discussed. On the face of it, the use of a large set of registers should decrease the need to access memory. The design task is to organize the registers in such a fashion that this goal is realized. Read page 507 – 510 for a detailed explanation. Compiler-based register optimization   Reduced Instructions Set Architecture There are two advantages to smaller programs… Because the program takes up less memory, there is a savings in that resource (this was more compelling when memory was more expensive) Smaller programs should improve performance, and this will happen in two ways – fewer instructions means fewer instruction bytes to be fetched and in a paging environment smaller programs occupy fewer pages, reducing page faults. Certain characteristics are common to RISC processors… One instruction per cycle Register-to-register operations Simple addressing modes Simple instruction formats RISC vs. CISC After initial enthusiasm for RISC machines, there has been a growing realization that RISC designs may benefit from the inclusion of some CISC features CISC designs may benefit from the inclusion of some RISC features

    Read the article

  • How to interpret the contents of /proc/bus/pci/devices ?

    - by vivekian2
    The first few fields of 'cat /proc/bus/pci/devices' are understandable. Field 1 - BusDevFunc Field 2 - Vendor Id + Device Id Field 3 - Interrupt Line Field 4 - BAR 0 and the rest of the BAR registers (0 - 5) after that. After the BAR registers are printed out, what are the other fields? Specifically, what PCI configuration space registers(offsets) are printed out?

    Read the article

  • HLSL: Enforce Constant Register Limit at Compile Time

    - by Andrew Russell
    In HLSL, is there any way to limit the number of constant registers that the compiler uses? Specifically, if I have something like: float4 foobar[300]; In a vs_2_0 vertex shader, the compiler will merrily generate the effect with more than 256 constant registers. But a 2.0 vertex shader is only guaranteed to have access to 256 constant registers, so when I try to use the effect, it fails in an obscure and GPU-dependent way at runtime. I would much rather have it fail at compile time. This problem is especially annoying as the compiler itself allocates constant registers behind the scenes, on top of the ones I am asking for. I have to check the assembly to see if I'm over the limit. Ideally I'd like to do this in HLSL (I'm using the XNA content pipeline), but if there's a flag that can be passed to the compiler that would also be interesting.

    Read the article

  • Only One GPU Detected in the Nvidia Quadra NVS 450

    - by Kyle Brandt
    I just built myself an new workstation and now only 2 of 3 monitors are working. I built the nvidia driver by downloading it and installing with ./Nvidia... Before when I ran nvidia-settings I saw two GPUs listed but now I only see one. Xorg Config (Not sure how I ended up with 3 devices in there): # nvidia-settings: X configuration file generated by nvidia-settings # nvidia-settings: version 256.35 (buildmeister@builder101) Wed Jun 16 19:25:39 PDT 2010 Section "ServerLayout" # Removed Option "Xinerama" "1" Identifier "Layout0" Screen 0 "Screen0" 0 0 Screen 1 "Screen1" RightOf "Screen0" InputDevice "Keyboard0" "CoreKeyboard" InputDevice "Mouse0" "CorePointer" Option "Xinerama" "0" EndSection Section "Files" EndSection Section "InputDevice" # generated from default Identifier "Mouse0" Driver "mouse" Option "Protocol" "auto" Option "Device" "/dev/psaux" Option "Emulate3Buttons" "no" Option "ZAxisMapping" "4 5" EndSection Section "InputDevice" # generated from default Identifier "Keyboard0" Driver "kbd" EndSection Section "Monitor" # HorizSync source: edid, VertRefresh source: edid Identifier "Monitor0" VendorName "Unknown" ModelName "DELL E207WFP" HorizSync 30.0 - 83.0 VertRefresh 56.0 - 75.0 Option "DPMS" EndSection Section "Monitor" # HorizSync source: edid, VertRefresh source: edid Identifier "Monitor1" VendorName "Unknown" ModelName "DELL E207WFP" HorizSync 30.0 - 83.0 VertRefresh 56.0 - 75.0 Option "DPMS" EndSection Section "Monitor" # HorizSync source: edid, VertRefresh source: edid Identifier "Monitor2" VendorName "Unknown" ModelName "DELL E207WFP" HorizSync 30.0 - 83.0 VertRefresh 56.0 - 75.0 Option "DPMS" EndSection Section "Device" Identifier "Device0" Driver "nvidia" VendorName "NVIDIA Corporation" BoardName "Quadro NVS 450" BusID "PCI:6:0:0" EndSection Section "Device" Identifier "Device1" Driver "nvidia" VendorName "NVIDIA Corporation" BoardName "Quadro NVS 450" BusID "PCI:5:0:0" EndSection Section "Device" Identifier "Device2" Driver "nvidia" VendorName "NVIDIA Corporation" BoardName "Quadro NVS 450" BusID "PCI:3:0:0" EndSection Section "Screen" # Removed Option "TwinView" "0" # Removed Option "metamodes" "DFP-0: nvidia-auto-select +0+0" # Removed Option "metamodes" "DFP-0: nvidia-auto-select +0+275, DFP-3: nvidia-auto-select +1680+0" Identifier "Screen0" Device "Device0" Monitor "Monitor0" DefaultDepth 24 Option "TwinView" "1" Option "TwinViewXineramaInfoOrder" "DFP-3" Option "metamodes" "DFP-0: nvidia-auto-select +0+0, DFP-3: nvidia-auto-select +1680+0" SubSection "Display" Depth 24 EndSubSection EndSection Section "Screen" # Removed Option "metamodes" "DFP-3: nvidia-auto-select +0+0" Identifier "Screen1" Device "Device1" Monitor "Monitor1" DefaultDepth 24 Option "TwinView" "0" Option "metamodes" "nvidia-auto-select +0+0" SubSection "Display" Depth 24 EndSubSection EndSection Section "Screen" Identifier "Screen2" Device "Device2" Monitor "Monitor2" DefaultDepth 24 Option "TwinView" "0" Option "metamodes" "nvidia-auto-select +0+0" SubSection "Display" Depth 24 EndSubSection EndSection lscpi: 00:00.0 Host bridge: Intel Corporation 5520/5500/X58 I/O Hub to ESI Port (rev 13) 00:01.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 1 (rev 13) 00:02.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 2 (rev 13) 00:03.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 3 (rev 13) 00:10.0 PIC: Intel Corporation 5520/5500/X58 Physical and Link Layer Registers Port 0 (rev 13) 00:10.1 PIC: Intel Corporation 5520/5500/X58 Routing and Protocol Layer Registers Port 0 (rev 13) 00:11.0 PIC: Intel Corporation 5520/5500 Physical and Link Layer Registers Port 1 (rev 13) 00:11.1 PIC: Intel Corporation 5520/5500 Routing & Protocol Layer Register Port 1 (rev 13) 00:13.0 PIC: Intel Corporation 5520/5500/X58 I/O Hub I/OxAPIC Interrupt Controller (rev 13) 00:14.0 PIC: Intel Corporation 5520/5500/X58 I/O Hub System Management Registers (rev 13) 00:14.1 PIC: Intel Corporation 5520/5500/X58 I/O Hub GPIO and Scratch Pad Registers (rev 13) 00:14.2 PIC: Intel Corporation 5520/5500/X58 I/O Hub Control Status and RAS Registers (rev 13) 00:15.0 PIC: Intel Corporation 5520/5500/X58 Trusted Execution Technology Registers (rev 13) 00:1a.0 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #4 00:1a.1 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #5 00:1a.2 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #6 00:1a.7 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #2 00:1b.0 Audio device: Intel Corporation 82801JI (ICH10 Family) HD Audio Controller 00:1c.0 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 1 00:1c.1 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 2 00:1c.3 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 4 00:1c.4 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 5 00:1d.0 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #1 00:1d.1 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #2 00:1d.2 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #3 00:1d.7 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #1 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90) 00:1f.0 ISA bridge: Intel Corporation 82801JIR (ICH10R) LPC Interface Controller 00:1f.2 IDE interface: Intel Corporation 82801JI (ICH10 Family) 4 port SATA IDE Controller #1 00:1f.3 SMBus: Intel Corporation 82801JI (ICH10 Family) SMBus Controller 00:1f.5 IDE interface: Intel Corporation 82801JI (ICH10 Family) 2 port SATA IDE Controller #2 01:00.0 IDE interface: Device 1b4b:91a3 (rev 11) 02:00.0 USB Controller: NEC Corporation Device 0194 (rev 03) 03:00.0 PCI bridge: nVidia Corporation PCI express bridge for Quadro Plex S4 / Tesla S870 / Tesla S1070 (rev a3) 04:00.0 PCI bridge: nVidia Corporation PCI express bridge for Quadro Plex S4 / Tesla S870 / Tesla S1070 (rev a3) 04:02.0 PCI bridge: nVidia Corporation PCI express bridge for Quadro Plex S4 / Tesla S870 / Tesla S1070 (rev a3) 05:00.0 3D controller: nVidia Corporation G98 [Quadro NVS 450] (rev a1) 06:00.0 VGA compatible controller: nVidia Corporation G98 [Quadro NVS 450] (rev a1) 08:00.0 SATA controller: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 02) 08:00.1 IDE interface: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 02) 09:00.0 SATA controller: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) 09:00.1 IDE interface: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) 0a:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 06) 0b:06.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)

    Read the article

  • Only One GPU Detected in the Nvidia Quadro NVS 450

    - by Kyle Brandt
    I just built myself an new workstation and now only 2 of 3 monitors are working. I built the nvidia driver by downloading it and installing with ./Nvidia... Before when I ran nvidia-settings I saw two GPUs listed but now I only see one. Xorg Config (Not sure how I ended up with 3 devices in there): # nvidia-settings: X configuration file generated by nvidia-settings # nvidia-settings: version 256.35 (buildmeister@builder101) Wed Jun 16 19:25:39 PDT 2010 Section "ServerLayout" # Removed Option "Xinerama" "1" Identifier "Layout0" Screen 0 "Screen0" 0 0 Screen 1 "Screen1" RightOf "Screen0" InputDevice "Keyboard0" "CoreKeyboard" InputDevice "Mouse0" "CorePointer" Option "Xinerama" "0" EndSection Section "Files" EndSection Section "InputDevice" # generated from default Identifier "Mouse0" Driver "mouse" Option "Protocol" "auto" Option "Device" "/dev/psaux" Option "Emulate3Buttons" "no" Option "ZAxisMapping" "4 5" EndSection Section "InputDevice" # generated from default Identifier "Keyboard0" Driver "kbd" EndSection Section "Monitor" # HorizSync source: edid, VertRefresh source: edid Identifier "Monitor0" VendorName "Unknown" ModelName "DELL E207WFP" HorizSync 30.0 - 83.0 VertRefresh 56.0 - 75.0 Option "DPMS" EndSection Section "Monitor" # HorizSync source: edid, VertRefresh source: edid Identifier "Monitor1" VendorName "Unknown" ModelName "DELL E207WFP" HorizSync 30.0 - 83.0 VertRefresh 56.0 - 75.0 Option "DPMS" EndSection Section "Monitor" # HorizSync source: edid, VertRefresh source: edid Identifier "Monitor2" VendorName "Unknown" ModelName "DELL E207WFP" HorizSync 30.0 - 83.0 VertRefresh 56.0 - 75.0 Option "DPMS" EndSection Section "Device" Identifier "Device0" Driver "nvidia" VendorName "NVIDIA Corporation" BoardName "Quadro NVS 450" BusID "PCI:6:0:0" EndSection Section "Device" Identifier "Device1" Driver "nvidia" VendorName "NVIDIA Corporation" BoardName "Quadro NVS 450" BusID "PCI:5:0:0" EndSection Section "Device" Identifier "Device2" Driver "nvidia" VendorName "NVIDIA Corporation" BoardName "Quadro NVS 450" BusID "PCI:3:0:0" EndSection Section "Screen" # Removed Option "TwinView" "0" # Removed Option "metamodes" "DFP-0: nvidia-auto-select +0+0" # Removed Option "metamodes" "DFP-0: nvidia-auto-select +0+275, DFP-3: nvidia-auto-select +1680+0" Identifier "Screen0" Device "Device0" Monitor "Monitor0" DefaultDepth 24 Option "TwinView" "1" Option "TwinViewXineramaInfoOrder" "DFP-3" Option "metamodes" "DFP-0: nvidia-auto-select +0+0, DFP-3: nvidia-auto-select +1680+0" SubSection "Display" Depth 24 EndSubSection EndSection Section "Screen" # Removed Option "metamodes" "DFP-3: nvidia-auto-select +0+0" Identifier "Screen1" Device "Device1" Monitor "Monitor1" DefaultDepth 24 Option "TwinView" "0" Option "metamodes" "nvidia-auto-select +0+0" SubSection "Display" Depth 24 EndSubSection EndSection Section "Screen" Identifier "Screen2" Device "Device2" Monitor "Monitor2" DefaultDepth 24 Option "TwinView" "0" Option "metamodes" "nvidia-auto-select +0+0" SubSection "Display" Depth 24 EndSubSection EndSection lscpi: 00:00.0 Host bridge: Intel Corporation 5520/5500/X58 I/O Hub to ESI Port (rev 13) 00:01.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 1 (rev 13) 00:02.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 2 (rev 13) 00:03.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 3 (rev 13) 00:10.0 PIC: Intel Corporation 5520/5500/X58 Physical and Link Layer Registers Port 0 (rev 13) 00:10.1 PIC: Intel Corporation 5520/5500/X58 Routing and Protocol Layer Registers Port 0 (rev 13) 00:11.0 PIC: Intel Corporation 5520/5500 Physical and Link Layer Registers Port 1 (rev 13) 00:11.1 PIC: Intel Corporation 5520/5500 Routing & Protocol Layer Register Port 1 (rev 13) 00:13.0 PIC: Intel Corporation 5520/5500/X58 I/O Hub I/OxAPIC Interrupt Controller (rev 13) 00:14.0 PIC: Intel Corporation 5520/5500/X58 I/O Hub System Management Registers (rev 13) 00:14.1 PIC: Intel Corporation 5520/5500/X58 I/O Hub GPIO and Scratch Pad Registers (rev 13) 00:14.2 PIC: Intel Corporation 5520/5500/X58 I/O Hub Control Status and RAS Registers (rev 13) 00:15.0 PIC: Intel Corporation 5520/5500/X58 Trusted Execution Technology Registers (rev 13) 00:1a.0 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #4 00:1a.1 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #5 00:1a.2 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #6 00:1a.7 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #2 00:1b.0 Audio device: Intel Corporation 82801JI (ICH10 Family) HD Audio Controller 00:1c.0 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 1 00:1c.1 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 2 00:1c.3 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 4 00:1c.4 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 5 00:1d.0 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #1 00:1d.1 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #2 00:1d.2 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #3 00:1d.7 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #1 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90) 00:1f.0 ISA bridge: Intel Corporation 82801JIR (ICH10R) LPC Interface Controller 00:1f.2 IDE interface: Intel Corporation 82801JI (ICH10 Family) 4 port SATA IDE Controller #1 00:1f.3 SMBus: Intel Corporation 82801JI (ICH10 Family) SMBus Controller 00:1f.5 IDE interface: Intel Corporation 82801JI (ICH10 Family) 2 port SATA IDE Controller #2 01:00.0 IDE interface: Device 1b4b:91a3 (rev 11) 02:00.0 USB Controller: NEC Corporation Device 0194 (rev 03) 03:00.0 PCI bridge: nVidia Corporation PCI express bridge for Quadro Plex S4 / Tesla S870 / Tesla S1070 (rev a3) 04:00.0 PCI bridge: nVidia Corporation PCI express bridge for Quadro Plex S4 / Tesla S870 / Tesla S1070 (rev a3) 04:02.0 PCI bridge: nVidia Corporation PCI express bridge for Quadro Plex S4 / Tesla S870 / Tesla S1070 (rev a3) 05:00.0 3D controller: nVidia Corporation G98 [Quadro NVS 450] (rev a1) 06:00.0 VGA compatible controller: nVidia Corporation G98 [Quadro NVS 450] (rev a1) 08:00.0 SATA controller: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 02) 08:00.1 IDE interface: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 02) 09:00.0 SATA controller: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) 09:00.1 IDE interface: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) 0a:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 06) 0b:06.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)

    Read the article

< Previous Page | 1 2 3 4 5 6 7 8 9 10 11 12  | Next Page >