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  • Generating %pc relative address of constant data

    - by Hudson
    Is there a way to have gcc generate %pc relative addresses of constants? Even when the string appears in the text segment, arm-elf-gcc will generate a constant pointer to the data, load the address of the pointer via a %pc relative address and then dereference it. For a variety of reasons, I need to skip the middle step. As an example, this simple function: const char * filename(void) { static const char _filename[] __attribute__((section(".text"))) = "logfile"; return _filename; } generates (when compiled with arm-elf-gcc-4.3.2 -nostdlib -c -O3 -W -Wall logfile.c): 00000000 <filename>: 0: e59f0000 ldr r0, [pc, #0] ; 8 <filename+0x8> 4: e12fff1e bx lr 8: 0000000c .word 0x0000000c 0000000c <_filename.1175>: c: 66676f6c .word 0x66676f6c 10: 00656c69 .word 0x00656c69 I would have expected it to generate something more like: filename: add r0, pc, #0 bx lr _filename.1175: .ascii "logfile\000" The code in question needs to be partially position independent since it will be relocated in memory at load time, but also integrate with code that was not compiled -fPIC, so there is no global offset table. My current work around is to call a non-inline function (which will be done via a %pc relative address) to find the offset from the compiled location in a technique similar to how -fPIC code works: static intptr_t __attribute__((noinline)) find_offset( void ) { uintptr_t pc; asm __volatile__ ( "mov %0, %%pc" : "=&r"(pc) ); return pc - 8 - (uintptr_t) find_offset; } But this technique requires that all data references be fixed up manually, so the filename() function in the above example would become: const char * filename(void) { static const char _filename[] __attribute__((section(".text"))) = "logfile"; return _filename + find_offset(); }

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  • When does an ARM7 processor increase its PC register?

    - by Summer_More_More_Tea
    Hi everyone: I'm thinking about this question for a time: when does an ARM7(with 3 pipelines) processor increase its PC register. I originally thought that after an instruction has been executed, the processor first check is there any exception in the last execution, then increase PC by 2 or 4 depending on current state. If an exception occur, ARM7 will change its running mode, store PC in the LR of current mode and begin to process current exception without modifying the PC register. But it make no sense when analyzing returning instructions. I can not work out why PC will be assigned LR when returning from an undefined-instruction-exception while LR-4 from prefetch-abort-exception, don't both of these exceptions happened at the decoding state? What's more, according to my textbook, PC will always be assigned LR-4 when returning from prefetch-abort-exception no matter what state the processor is(ARM or Thumb) before exception occurs. However, I think PC should be assigned LR-2 if the original state is Thumb, since a Thumb-instruction is 2 bytes long instead of 4 bytes which an ARM-instruction holds, and we just wanna roll-back an instruction in current state. Is there any flaws in my reasoning or something wrong with the textbook. Seems a long question. I really hope anyone can help me get the right answer. Thanks in advance.

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  • writing to an ioport resulting in segfaults...

    - by Sniperchild
    I'm writing for an atmel at91sam9260 arm 9 cored single board computer [glomation gesbc9260] Using request_mem_region(0xFFFFFC00,0x100,"name"); //port range runs from fc00 to fcff that works fine and shows up in /proc/iomem then i try to write to the last bit of the port at fc20 with writel(0x1, 0xFFFFFC20); and i segfault...specifically "unable to handle kernel paging request at virtual address fffffc20. I'm of the mind that i'm not allocating the right memory space... any helpful insight would be great...

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  • Adding libraries to a project in xcode - symbols not found

    - by kudorgyozo
    I am trying to make an iphone app in xcode that uses pjsip. The problem is I don't know how to link the libraries. I have the ARM version of the libraries in this folder in mac os x. /Users/kudorgyozo/pjsip_iphone In Xcode: I have specified the library and header search paths like this: for includes: /Users/kudorgyozo/pjsip_iphone/pjlib/include /Users/kudorgyozo/pjsip_iphone/pjlib-util/include /Users/kudorgyozo/pjsip_iphone/pjmedia/include /Users/kudorgyozo/pjsip_iphone/pjnath/include /Users/kudorgyozo/pjsip_iphone/pjsip/include for libraries: /Users/kudorgyozo/pjsip_iphone/pjlib/lib /Users/kudorgyozo/pjsip_iphone/pjlib-util/lib /Users/kudorgyozo/pjsip_iphone/pjmedia/lib /Users/kudorgyozo/pjsip_iphone/pjnath/lib /Users/kudorgyozo/pjsip_iphone/pjsip/lib and then using the "Other linker flags" : -lpj-arm-apple-darwin9 -lpjlib-util-arm-apple-darwin9 -lpjmedia-arm-apple-darwin9 -lpjmedia-audiodev-arm-apple-darwin9 -lpjmedia-codec-arm-apple-darwin9 -lpjsdp-arm-apple-darwin9 -lpjnath-arm-apple-darwin9 -lpjsip-arm-apple-darwin9 -lpjsip-simple-arm-apple-darwin9 -lpjsip-ua-arm-apple-darwin9 -lpjsua-arm-apple-darwin9 Is this OK like this? Because it gives me symbol(s) not found errors. I think no symbol is found from the "included" libraries. I don't know what is wrong i'm just beginning to understand how building an app works under linux based systems i've only done programming in C# before.

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  • VFP Unit Matrix Multiply problem on the iPhone

    - by Ian Copland
    Hi. I'm trying to write a Matrix3x3 multiply using the Vector Floating Point on the iPhone, however i'm encountering some problems. This is my first attempt at writing any ARM assembly, so it could be a faily simple solution that i'm not seeing. I've currently got a small application running using a maths library that i've written. I'm investigating into the benifits using the Vector Floating Point Unit would provide so i've taken my matrix multiply and converted it to asm. Previously the application would run without a problem, however now my objects will all randomly disappear. This seems to be caused by the results from my matrix multiply becoming NAN at some point. Heres the code IMatrix3x3 operator*(IMatrix3x3 & _A, IMatrix3x3 & _B) { IMatrix3x3 C; //C++ code for the simulator #if TARGET_IPHONE_SIMULATOR == true C.A0 = _A.A0 * _B.A0 + _A.A1 * _B.B0 + _A.A2 * _B.C0; C.A1 = _A.A0 * _B.A1 + _A.A1 * _B.B1 + _A.A2 * _B.C1; C.A2 = _A.A0 * _B.A2 + _A.A1 * _B.B2 + _A.A2 * _B.C2; C.B0 = _A.B0 * _B.A0 + _A.B1 * _B.B0 + _A.B2 * _B.C0; C.B1 = _A.B0 * _B.A1 + _A.B1 * _B.B1 + _A.B2 * _B.C1; C.B2 = _A.B0 * _B.A2 + _A.B1 * _B.B2 + _A.B2 * _B.C2; C.C0 = _A.C0 * _B.A0 + _A.C1 * _B.B0 + _A.C2 * _B.C0; C.C1 = _A.C0 * _B.A1 + _A.C1 * _B.B1 + _A.C2 * _B.C1; C.C2 = _A.C0 * _B.A2 + _A.C1 * _B.B2 + _A.C2 * _B.C2; //VPU ARM asm for the device #else //create a pointer to the Matrices IMatrix3x3 * pA = &_A; IMatrix3x3 * pB = &_B; IMatrix3x3 * pC = &C; //asm code asm volatile( //turn on a vector depth of 3 "fmrx r0, fpscr \n\t" "bic r0, r0, #0x00370000 \n\t" "orr r0, r0, #0x00020000 \n\t" "fmxr fpscr, r0 \n\t" //load matrix B into the vector bank "fldmias %1, {s8-s16} \n\t" //load the first row of A into the scalar bank "fldmias %0!, {s0-s2} \n\t" //calulate C.A0, C.A1 and C.A2 "fmuls s17, s8, s0 \n\t" "fmacs s17, s11, s1 \n\t" "fmacs s17, s14, s2 \n\t" //save this into the output "fstmias %2!, {s17-s19} \n\t" //load the second row of A into the scalar bank "fldmias %0!, {s0-s2} \n\t" //calulate C.B0, C.B1 and C.B2 "fmuls s17, s8, s0 \n\t" "fmacs s17, s11, s1 \n\t" "fmacs s17, s14, s2 \n\t" //save this into the output "fstmias %2!, {s17-s19} \n\t" //load the third row of A into the scalar bank "fldmias %0!, {s0-s2} \n\t" //calulate C.C0, C.C1 and C.C2 "fmuls s17, s8, s0 \n\t" "fmacs s17, s11, s1 \n\t" "fmacs s17, s14, s2 \n\t" //save this into the output "fstmias %2!, {s17-s19} \n\t" //set the vector depth back to 1 "fmrx r0, fpscr \n\t" "bic r0, r0, #0x00370000 \n\t" "orr r0, r0, #0x00000000 \n\t" "fmxr fpscr, r0 \n\t" //pass the inputs and set the clobber list : "+r"(pA), "+r"(pB), "+r" (pC) : :"cc", "memory","s0", "s1", "s2", "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19" ); #endif return C; } As far as i can see that makes sence. While debugging i've managed to notice that if i were to say _A = C prior to the return and after the ASM, _A will not necessarily be equal to C which has only increased my confusion. I had thought it was possibly due to the pointers I'm giving to the VFPU being incrimented by lines such as "fldmias %0!, {s0-s2} \n\t" however my understanding of asm is not good enough to properly understand the problem, nor to see an alternative approach to that line of code. Anyway, I was hoping someone with a greater understanding than me would be able to see a solution, and any help would be greatly appreciated, thank you :-)

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  • Low level qemu based debugging

    - by Dacav
    I've to test some low level code on an ARM architecture. Typically experimentation is quite complicated on the real board, so I was thinking about QEMU. What I'd like to get is some kind of debugging information like printfs or gdb. I know that this is simple with linux since it implements both the device driver for the QEMU Integrator and the gdb feature, but I'm not working with Linux. Also I suspect that extracting this kind of functionality from the Linux kernel source code would be complicated. I'm searching from some simple operating system that already implements one of those features. Do you have some advice? Thanks in advance.

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  • A JTAG emulator for use with a Hawkboard and OpenOCD?

    - by David Brown
    I'd like to try bare metal ARM programming with the Hawkboard, but the deployment process looks awful. I'm totally new to this, so I could be misunderstanding the instructions, but it appears that I have to use a program called AISgen to convert the binary file, then boot with u-Boot over UART and copy the AIS binary into memory. Not only is that a lot of stuff to do every time I make a change, it also doesn't give me the ability to debug with GDB. The best solution for this that I can find is JTAG. But the prices for these JTAG emulators look ridiculous. I'm not even sure which ones will work with the Hawkboard and which ones won't. So far, my best bet appears to be the Flyswatter, but the pin layout is different. Basically, I need something that's relatively cheap and works with the Hawkboard and OpenOCD. Any suggestions? Or is there another way I could do this, perhaps?

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  • IAR Embedded Workbench - setting endian-ness of variable

    - by Seidleroni
    I'm using IAR Embedded Workbench for ARM (ARM7TDMI-S) and the majority of my work is done using little-endian format. However, I saw in the manual that I can do something like : __big_endian int i, j; to declare those two variables as big endian (while the rest of the app as little endian). This seems like a fantastic feature, but when I try to compile, I always get the errror: Error[Pa002]: the type attribute "__big_endian" is not allowed on this declaration. The big endian line above is copied directly from the manual, but it does not work. This is a great feature of the compiler and would make life a big easier. Any ideas how to get it working? I have my language conformance set to 'Allow IAR extensions' on the C/C++ Compiler options tab on the IDE options.

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  • Getting SIGILL in float to fixed conversion

    - by foliveira
    I'm receiving a SIGILL after running the following code. I can't really figure what's wrong with it. The target platform is ARM, and I'm trying to port a known library (in which this code is contained) void convertFloatToFixed(float nX, float nY, unsigned int &nFixed) { short sx = (short) (nX * 32); short sy = (short) (nY * 32); unsigned short *ux = (unsigned short*) &sx; unsigned short *uy = (unsigned short*) &sy; nFixed = (*ux << 16) | *uy; } Any help on it would be greatly appreciated. Thanks in advance

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  • Potential problems porting to different architectures

    - by Brendan Long
    I'm writing a Linux program that currently compiles and works fine on x86 and x86_64, and now I'm wondering if there's anything special I'll need to do to make it work on other architectures. What I've heard is that for cross platform code I should: Don't assume anything about the size of a pointer, int or size_t Don't make assumptions about byte order (I don't do any bit shifting -- I assume gcc will optimize my power of two multiplication/division for me) Don't use assembly blocks (obvious) Make sure your libraries work (I'm using SQLite, libcurl and Boost, which all seem pretty cross-platform) Is there anything else I need to worry about? I'm not currently targeting any other architectures, but I expect to support ARM at some point, and I figure I might as well make it work on any architecture if I can. Also, regarding my second point about byte order, do I need to do anything special with text input? I read files with getline(), so it seems like that should be done automatically as well.

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  • Get the default link configuration gcc uses when calling the linker.

    - by witkamp
    I am using the CodeSorcery arm-eabi-gcc tool chain and I have a problem using ld separate from gcc I can compile my simple program and link it, if I let gcc call the ld. This works not problem g++ test.cpp; # Works This does not work because of missing symbols g++ -c test.cpp ld -o test crti.o crtbegin.o test.o crtend.o crtn.o -lgcc -lc -lstdc++; # Fails Notice I am adding the gcc libraries to the ld command What am I missing? Also if there is a better way to make configuring ld to using the default gcc linking? Thanks

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  • Preventing objects from being linked if they are not needed?

    - by Massif
    I have an ARM project that I'm building with make. I'm creating the list of object files to link based on the names of all of the .c and .cpp files in my source directory. However, I would like to exclude objects from being linked if they are never used. Will the linker exclude these objects from the .elf file automatically even if I include them in the list of objects to link? If not, is there a way to generate a list of only the objects that need to be linked?

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  • super-space-optimized code

    - by Will
    There are key self-contained algorithms - particularly cryptography-related such as AES, RSA, SHA1 etc - which you can find many implementations of for free on the internet. Some are written to be nice and portable clean C. Some are written to be fast - often with macros, and explicit unrolling. As far as I can tell, none are trying to be especially super-small - so I'm resigned to writing my own - explicitly AES128 decryption and SHA1 for ARM THUMB2. What patterns and tricks can I use to do so? Are there compilers/tools that can roll-up code?

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  • How to get the most out of the book 'Practical Reverse Engineering: x86, x64, ARM, Windows Kernel, Reversing Tools, and Obfuscation'? [on hold]

    - by user3565816
    I was reading the book Practical Reverse Engineering: x86, x64, ARM, Windows Kernel, Reversing Tools, and Obfuscation by Bruce Dang et. al, as I am interested in learning about Reverse Engineering. However I found that most of what I was reading made very little sense to me and I felt confused. So my question is, what material should I go through first before returning to this book so that I can get the most out of it? Thanks in advance for your assistance.

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  • memory alignment within gcc structs

    - by Mumbles
    I am porting an application to an ARM platform in C, the application also runs on an x86 processor, and must be backward compatible. I am now having some issues with variable alignment. I have read the gcc manual for __attribute__((aligned(4),packed)) I interpret what is being said as the start of the struct is aligned to the 4 byte boundry and the inside remains untouched because of the packed statement. originally I had this but occasionally it gets placed unaligned with the 4 byte boundary. typedef struct { unsigned int code; unsigned int length; unsigned int seq; unsigned int request; unsigned char nonce[16]; unsigned short crc; } __attribute__((packed)) CHALLENGE; so I change it to this. typedef struct { unsigned int code; unsigned int length; unsigned int seq; unsigned int request; unsigned char nonce[16]; unsigned short crc; } __attribute__((aligned(4),packed)) CHALLENGE; The understand I stated earlier seems to be incorrect as both the struct is now aligned to a 4 byte boundary, and and the inside data is now aligned to a four byte boundary, but because of the endianess, the size of the struct has increased in size from 42 to 44 bytes. This size is critical as we have other applications that depend on the struct being 42 bytes. Could some describe to me how to perform the operation that I require. Any help is much appreciated.

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  • What is the official Microsoft name for Windows 8 versions: Intel compatible vs. ARM?

    - by Clay Nichols
    Windows 8 will, AFAIK, be available in two very different flavors: One that supports old Windows programs (intel processor, I think) and the other will be an ARM processor which does NOT support x86 programs. I need to know how to refer to these to let customers clearly know which version of Windows we (currently) support. It looks like the terminology is: Windows 8 : This will be backward compatible with Win 32 apps. Windows RT: Runs on ARM-based processor devices (probably mainly tablets) and does not support

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  • Problem calling linux C code from FIQ handler

    - by fastmonkeywheels
    I'm working on an armv6 core and have an FIQ hander that works great when I do all of my work in it. However I need to branch to some additional code that's too large for the FIQ memory area. The FIQ handler gets copied from fiq_start to fiq_end to 0xFFFF001C when registered static void test_fiq_handler(void) { asm volatile("\ .global fiq_start\n\ fiq_start:"); // clear gpio irq asm("ldr r10, GPIO_BASE_ISR"); asm("ldr r9, [r10]"); asm("orr r9, #0x04"); asm("str r9, [r10]"); // clear force register asm("ldr r10, AVIC_BASE_INTFRCH"); asm("ldr r9, [r10]"); asm("mov r9, #0"); asm("str r9, [r10]"); // prepare branch register asm(" ldr r11, fiq_handler"); // save all registers, build sp and branch to C asm(" adr r9, regpool"); asm(" stmia r9, {r0 - r8, r14}"); asm(" adr sp, fiq_sp"); asm(" ldr sp, [sp]"); asm(" add lr, pc,#4"); asm(" mov pc, r11"); #if 0 asm("ldr r10, IOMUX_ADDR12"); asm("ldr r9, [r10]"); asm("orr r9, #0x08 @ top/vertex LED"); asm("str r9,[r10] @turn on LED"); asm("bic r9, #0x08 @ top/vertex LED"); asm("str r9,[r10] @turn on LED"); #endif asm(" adr r9, regpool"); asm(" ldmia r9, {r0 - r8, r14}"); // return asm("subs pc, r14, #4"); asm("IOMUX_ADDR12: .word 0xFC2A4000"); asm("AVIC_BASE_INTCNTL: .word 0xFC400000"); asm("AVIC_BASE_INTENNUM: .word 0xFC400008"); asm("AVIC_BASE_INTDISNUM: .word 0xFC40000C"); asm("AVIC_BASE_FIVECSR: .word 0xFC400044"); asm("AVIC_BASE_INTFRCH: .word 0xFC400050"); asm("GPIO_BASE_ISR: .word 0xFC2CC018"); asm(".globl fiq_handler"); asm("fiq_sp: .long fiq_stack+120"); asm("fiq_handler: .long 0"); asm("regpool: .space 40"); asm(".pool"); asm(".align 5"); asm("fiq_stack: .space 124"); asm(".global fiq_end"); asm("fiq_end:"); } fiq_hander gets set to the following function: static void fiq_flip_pins(void) { asm("ldr r10, IOMUX_ADDR12_k"); asm("ldr r9, [r10]"); asm("orr r9, #0x08 @ top/vertex LED"); asm("str r9,[r10] @turn on LED"); asm("bic r9, #0x08 @ top/vertex LED"); asm("str r9,[r10] @turn on LED"); asm("IOMUX_ADDR12_k: .word 0xFC2A4000"); } EXPORT_SYMBOL(fiq_flip_pins); I know that since the FIQ handler operates outside of any normal kernel API's and that it is a rather high priority interrupt I must ensure that whatever I call is already swapped into memory. I do this by having the fiq_flip_pins function defined in the monolithic kernel and not as a module which gets vmalloc. If I don't branch to the fiq_flip_pins function, and instead do the work in the test_fiq_handler function everything works as expected. It's the branching that's causing me problems at the moment. Right after branching I get a kernel panic about a paging request. I don't understand why I'm getting the paging request. fiq_flip_pins is in the kernel at: c00307ec t fiq_flip_pins Unable to handle kernel paging request at virtual address 736e6f63 pgd = c3dd0000 [736e6f63] *pgd=00000000 Internal error: Oops: 5 [#1] PREEMPT Modules linked in: hello_1 CPU: 0 Not tainted (2.6.31-207-g7286c01-svn4 #122) PC is at strnlen+0x10/0x28 LR is at string+0x38/0xcc pc : [<c016b004>] lr : [<c016c754>] psr: a00001d3 sp : c3817ea0 ip : 736e6f63 fp : 00000400 r10: c03cab5c r9 : c0339ae0 r8 : 736e6f63 r7 : c03caf5c r6 : c03cab6b r5 : ffffffff r4 : 00000000 r3 : 00000004 r2 : 00000000 r1 : ffffffff r0 : 736e6f63 Flags: NzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment user Control: 00c5387d Table: 83dd0008 DAC: 00000015 Process sh (pid: 1663, stack limit = 0xc3816268) Stack: (0xc3817ea0 to 0xc3818000) Since there are no API calls in my code I have to assume that something is going wrong in the C call and back. Any help solving this is appreciated.

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  • Common SIMD techniques

    - by zxcat
    Hi! Where can I find information about common SIMD tricks? I have an instruction set and know, how to write non-tricky SIMD code, but I know, SIMD now is much more powerful. It can hold complex conditional branchless code. For example (ARMv6), the following sequence of instructions sets each byte of Rd equal to the unsigned minimum of the corresponding bytes of Ra and Rb: USUB8 Rd, Ra, Rb SEL Rd, Rb, Ra Links to tutorials / uncommon SIMD techniques are good too :) ARMv6 is the most interesting for me, but x86(SSE,...)/Neon(in ARMv7)/others are good too. Thank you.

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  • Trouble compiling libpng (& zlib) using RVCT 4.0's armcc compiler

    - by Arjun
    Hi, I'm trying to compile libpng & zlib using the RVCT 4.0 armcc compiler. However armcc cannot find 'fcntl.h', which I assume is a standard C library. Cygwin has fcntl.h (and the associated files types.h and _types.h), but when I use those, I get various compilation errors. Should I be using Cygwin's version of standard C libraries, or RVCT's? If the latter is correct, where do I get RVCT's versions of fcntl.h, types.h and _types.h? Thanks! Arjun

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  • error with "pmem.c" compiling linux source code for android

    - by Preetam
    I am compiling linux source code for android emulator. When i execute make command(for building and cross-compiling the linux source) i get the following error "pmem.c" file. root@ubuntu:~/common# make CHK include/linux/version.h CHK include/linux/utsrelease.h SYMLINK include/asm - include/asm-x86 CALL scripts/checksyscalls.sh CHK include/linux/compile.h CC drivers/misc/pmem.o drivers/misc/pmem.c:441: error: conflicting types for ‘phys_mem_access_prot’ /home/preetam/common/arch/x86/include/asm/pgtable.h:383: note: previous declaration of ‘phys_mem_access_prot’ was here drivers/misc/pmem.c: In function ‘flush_pmem_file’: drivers/misc/pmem.c:805: error: implicit declaration of function ‘dmac_flush_range’ drivers/misc/pmem.c: In function ‘pmem_setup’: drivers/misc/pmem.c:1265: error: implicit declaration of function ‘ioremap_cached’ drivers/misc/pmem.c:1266: warning: assignment makes pointer from integer without a cast make[2]: * [drivers/misc/pmem.o] Error 1 make[1]: [drivers/misc] Error 2 make: ** [drivers] Error 2 root@ubuntu:~/common# how to resolve this error. It seems that there may some problems in the "pmem.c" file and i'll have to choose different git repository. but that would be a very complex thing, as now i have already done most of the things till here. I might have to see correct version of this file. please someone tell what should i do? how to solve this errors. please help..thankyou!

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  • How does the linux kernel manage less than 1GB physical memory ?

    - by TheLoneJoker
    I'm learning the linux kernel internals and while reading "Understanding Linux Kernel", quite a few memory related questions struck me. One of them is, how the Linux kernel handles the memory mapping if the physical memory of say only 512 MB is installed on my system. As I read, kernel maps 0(or 16) MB-896MB physical RAM into 0xC0000000 linear address and can directly address it. So, in the above described case where I only have 512 MB: How can the kernel map 896 MB from only 512 MB ? What about user mode processes in this situation? Where are user mode processes in phys RAM? Every article explains only the situation, when you've installed 4 GB of memory and the kernel maps the 1 GB into kernel space and user processes uses the remaining amount of RAM. I would appreciate any help in improving my understanding. Thanks..!

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  • How does changing armv6/armv7 architecture to armv6 affect my iPad app? Will there be performance/st

    - by Flocked
    Hello, I need to change the the architectures of "Any iPhone OS Device" from "Optimized (armv6 armv7)" to "Standard (armv6)" for a library. I'm not exactly sure what effect will this have on the performance and stability of my iPad app. If I understand it right, the iPad has the armv7 architecture. I'm not so familiar with architectures, so I don't know what it means.

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  • ARMv6 FIQ, acknowledge interrupt

    - by fastmonkeywheels
    I'm working with an i.mx35 armv6 core processor. I have Interrupt 62 configured as a FIQ with my handler installed and being called. My handler at the moment just toggles an output pin so I can test latency with a scope. With the code below, once I trigger the FIQ it continues forever as fast as it can, apparently not being acknowledged. I'm triggering the FIQ by means of the Interrupt Force Register so I'm assured that the source isn't triggering it this fast. If I disable Interrupt 62 in the AVIC in my FIQ routine the interrupt only triggers once. I have read the sections on the VIC Port in the ARM1136JF-S and ARM1136J-S Technical Reference Manual and it covers proper exit procedure. I'm only having one FIQ handler so I have no need to branch. The line that I don't understand is: STR R0, [R8,#AckFinished] I'm not sure what AckFinished is supposed to be or what this command is supposed to do. My FIQ handler is below: ldr r9, IOMUX_ADDR12 ldr r8, [r9] orr r8, #0x08 @ top LED str r8,[r9] @turn on LED bic r8, #0x08 @ top LED str r8,[r9] @turn off LED subs pc, r14, #4 IOMUX_ADDR12: .word 0xFC2A4000 @remapped IOMUX addr My handler returns just fine and normal system operation resumes if I disable it after the first go, otherwise it triggers constantly and the system appears to hang. Do you think my assumption is right that the core isn't acknowledging the AVIC or could there be another cause of this FIQ triggering?

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