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Published on 2010-06-11T17:53:14Z
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2010/06/11
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Hello,
Anyone knows good enviroment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux?
Thanks Br
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I've got a problem with apt-get update and apt-get install ... commands .
every time update or installing fails and errors are :
Get:1 http://dl.google.com stable Release.gpg [198B]
Ign http://dl.google.com/linux/chrome/deb/ stable/main Translation-en_US
Get:2 http://dl…
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sh@ubuntu:/home/ccpp/helloworld$ make
gcc-4.6 -O2 -DMODULE -D_KERNEL_ -W -Wall -Wstrict-prototypes -Wmissing-prototypes -isystem /lib/modules/`uname -r`/build/include -c -o hello-1.o hello-1.c
hello-1.c:4:0: warning: "MODULE" redefined [enabled by default]
<command-line>:0:0: note: this is…
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I am having trouble accessing the several critical header files that show to be a part of the build process.
The "Ubuntu Software Center" shows "Build Essentials" as installed:
Next I did the following two commands, which did not improve the problem:
~$ sudo apt-get install build-essential
[sudo]…
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I'm trying to update my Debian machine to 2.6.32-46 (which is the new stable). However, after doing apt-get update my apt-cache search linux-image shows me:
linux-headers-2.6.32-5-486 - Header files for Linux 2.6.32-5-486
linux-headers-2.6.32-5-686-bigmem - Header files for Linux 2.6.32-5-686-bigmem
linux-headers-2…
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I'm helping out with a project for an embedded device that only has USB and no serial. This device is running Linux.
These days, when we need to connect to a serial port on a device we typically use a USB to serial adapter (on something like a phone system or a load balancing device, etc). I would…
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Hi,
When programming in VHDL, can you use a variable in a case statement? This variable will modified by one of the cases
i.e.
case task is
when 1 =>
when 2 =>
when number =>
is this OK?
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I am getting the warning that:
One or more signals are missing in the sensitivity list of always block.
always@(Address)begin
ReadData = instructMem[Address];
end
How do I get rid of this warning?
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I have pex_pkg.vhd and I want to use this library to make floating point adder but altera max+plus II give me an error can't open "PEX_lib" how to include this library in max+plus ?
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Hey,
Quick VHDL question, I don't have access to Xilinx at the moment due to dead laptop, so can't test this.
I was wondering if it's possible to use variables and arithmetic in 'downto' statements, e.g:
proc: process (x)
begin
y <= z(x downto 0) & z(7 downto x);
end process;
Thanks.
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Hi, i'm coding a 4-bit binary adder with accumulator:
library ieee;
use ieee.std_logic_1164.all;
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:inout bit;
done:out bit);
end binadder;
architecture binadder of binadder is
signal state:…
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